7904c6f0f3
The exclusive load/store instructions don't work well when MMU and cache are disabled on some cores e.g. Cortex-A72. Change it to voting lock[1] to select the primary core when multi-cores boot simultaneously. The voting lock has reasonable but minimal requirements on the memory system. [1] https://www.kernel.org/doc/html/next/arch/arm/vlocks.html Signed-off-by: Jaxson Han <jaxson.han@arm.com> |
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arc | ||
arm | ||
arm64 | ||
common | ||
mips | ||
nios2 | ||
posix | ||
riscv | ||
sparc | ||
x86 | ||
xtensa | ||
CMakeLists.txt | ||
Kconfig |