zephyr/soc
Carlo Caione 189cd1f4a2 cache: Rework cache API
The cache operations must be quick, optimized and possibly inlined. The
current API is clunky, functions are not inlined and passing parameters
around that are basically always known at compile time.

In this patch we rework the cache functions to allow us to get rid of
useless parameters and make inlining easier.

In particular this changeset is doing three things:

1. `CONFIG_HAS_ARCH_CACHE` is now `CONFIG_ARCH_CACHE` and
   `CONFIG_HAS_EXTERNAL_CACHE` is now `CONFIG_EXTERNAL_CACHE`

2. The cache API has been reworked.

3. Comments are added.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-12-01 13:40:56 -05:00
..
arc ARC: control shared (common) interrupts via IDU 2022-11-28 17:44:54 +01:00
arm cache: Rework cache API 2022-12-01 13:40:56 -05:00
arm64 boards/arm64: Add QEMU Virt KVM support 2022-11-17 11:16:08 +01:00
mips asm: update files with <zephyr/...> include prefix 2022-05-09 12:45:29 -04:00
nios2 linker: update files with <zephyr/...> include prefix 2022-05-09 12:45:29 -04:00
posix cmake: Update CONFIG_ASAN support 2022-08-19 08:30:01 +02:00
riscv soc: riscv: andes_v5: Fix system initialization for L2C 2022-11-29 09:50:05 +01:00
sparc linker: update files with <zephyr/...> include prefix 2022-05-09 12:45:29 -04:00
x86 soc: x86: Used fixed BDF values for early serial 2022-11-16 11:18:43 +01:00
xtensa intel_adsp: ace: power header update 2022-11-30 17:46:17 -05:00
Kconfig soc: Add ability for SOC to specify runtime CPU detection 2022-11-03 16:43:53 -04:00