Tomasz Leman 1c0c900cbb intel_adsp: ace15: Enhance HST domain power-down sequence ... This patch enhances the power-down sequence for the HOST (HST) domain within the Intel ADSP ACE 1.5 architecture. It introduces a check to ensure that a specific condition, represented by a magic key value, is met before disabling the HST domain. This additional verification step ensures that the HST domain is only powered down when it is safe to do so, thereby maintaining the stability and reliability of the system. Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>		2024-01-11 10:05:12 +01:00
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dc233c	xtensa: dc233c: force invalidating TLBs during page table swap	2023-12-27 15:59:05 +00:00
espressif_esp32	soc: espressif: add common linker tls entry	2024-01-08 15:09:48 +01:00
intel_adsp	intel_adsp: ace15: Enhance HST domain power-down sequence	2024-01-11 10:05:12 +01:00
nxp_adsp	xtensa: rename z_xtensa_irq to simple xtensa_irq	2023-12-13 09:41:24 +01:00
sample_controller	cmake: cleanup and simplify the standard include logic in Zephyr	2023-11-06 18:57:30 -05:00
CMakeLists.txt	soc/xtensa/intel_adsp: Upstream updates	2020-10-21 06:38:53 -04:00