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Mahesh Rao 80a863f947 tests: sip_svc: Add a stress test for sip_svc subsystem 
Add a stress test for sip_svc subsystem using
INTEL SOCFPGA AGILEX platform.

Signed-off-by: Mahesh Rao <mahesh.rao@intel.com>
2023-09-15 09:26:49 +02:00
..
intel_socfpga_agilex5_socdk.overlay tests: sip_svc: Add a stress test for sip_svc subsystem 2023-09-15 09:26:49 +02:00
intel_socfpga_agilex_socdk.overlay tests: sip_svc: Add a stress test for sip_svc subsystem 2023-09-15 09:26:49 +02:00