8db1a5add2
Removing the edge-trigger Kconfig as it is supported by default in the RISCV PLIC specifications. Define the edge-trigger register offset in the driver instead of retrieving the value from devicetree as it is not something configurable. The value 0x1080 is defined in Andes & Telink datasheets. Updated build_all testcase. Signed-off-by: Yong Cong Sin <ycsin@meta.com>
13 lines
396 B
Plaintext
13 lines
396 B
Plaintext
# Copyright (c) 2022 Carlo Caione <ccaione@baylibre.com>
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# SPDX-License-Identifier: Apache-2.0
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config PLIC
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bool "Platform Level Interrupt Controller (PLIC)"
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default y
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depends on DT_HAS_SIFIVE_PLIC_1_0_0_ENABLED
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select MULTI_LEVEL_INTERRUPTS
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select 2ND_LEVEL_INTERRUPTS
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help
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Platform Level Interrupt Controller provides support
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for external interrupt lines defined by the RISC-V SoC.
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