6e215ce6af
Add XIP support with MWDT toolchain. To have it proper tested add separate nsim platforms for XIP (flash + sram) and non-XIP (sram) memory organization in addition to existing nsim_hs platfor with CCMs (ICCM + DCCM) memory organization. This PR also enables MPU for all nsim hs3x based platforms (like we previously enabled it for qemu_arc_hs) to have proper memory regions permissions. Signed-off-by: Nikolay Agishev <agishev@synopsys.com>
30 lines
552 B
Plaintext
30 lines
552 B
Plaintext
/*
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* Copyright (c) 2022, Synopsys, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "skeleton.dtsi"
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#include <mem.h>
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#define DT_FLASH_SIZE DT_SIZE_M(4)
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#define DT_SRAM_SIZE DT_SIZE_M(4)
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/ {
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/* We are carving out of DRAM for a pseudo flash and sram region */
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flash0: flash@80000000 {
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compatible = "soc-nv-flash";
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reg = <0x80000000 DT_FLASH_SIZE>;
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};
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sram0: sram@80400000 {
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device_type = "memory";
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reg = <0x80400000 DT_SRAM_SIZE>;
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};
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chosen {
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zephyr,sram = &sram0;
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zephyr,flash = &flash0;
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};
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};
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