6abc5921e1
This commit introduces a driver for NXP's eDMA IP. The main reasons for introducing a new driver are the following: 1) The HAL EDMA wrappers don't support well different eDMA versions (e.g: i.MX93 and i.MX8QM). As such, a new revision had to be introduced, thus requiring a new Zephyr driver. 2) The eDMA versions found on i.MX93, i.MX8QM, and i.MX8QXP don't use the DMAMUX IP (instead, channel MUX-ing is performed through an eDMA register in the case of i.MX93). Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
35 lines
983 B
Plaintext
35 lines
983 B
Plaintext
# Copyright 2024 NXP
|
|
# SPDX-License-Identifier: Apache-2.0
|
|
|
|
config DMA_NXP_EDMA
|
|
bool "NXP enhanced Direct Memory Access (eDMA) driver"
|
|
default y
|
|
depends on DT_HAS_NXP_EDMA_ENABLED
|
|
help
|
|
Enable driver for NXP's eDMA IP.
|
|
|
|
if DMA_NXP_EDMA
|
|
|
|
config DMA_NXP_EDMA_ALIGN
|
|
int "Alignment (in bytes) required for the transfers"
|
|
default 8
|
|
help
|
|
Use this to set the alignment (in bytes)
|
|
used by entities employing this driver to
|
|
adjust the addresses and sizes of the memory
|
|
regions involved in the transfer process.
|
|
This value needs to match one of the possible
|
|
values for SSIZE and DSIZE, otherwise the
|
|
driver will return an error upon configuration.
|
|
|
|
config DMA_NXP_EDMA_ENABLE_HALFMAJOR_IRQ
|
|
bool "Set if CPU should be interrupted when CITER = BITER / 2"
|
|
default n
|
|
help
|
|
Enable this configuration if the CPU should be
|
|
interrupted when CITER = BITER / 2. Using this,
|
|
the CPU will be interrupted when CITER = BITER and
|
|
when CITER = BITER / 2.
|
|
|
|
endif # DMA_NXP_EDMA
|