bdfcd30513
Utilize a code spell-checking tool to scan for and correct spelling errors in all files within the dts/bindings/clock directory. Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
47 lines
842 B
YAML
47 lines
842 B
YAML
# Copyright (c) 2023 TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
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# SPDX-License-Identifier: Apache-2.0
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description: Renesas RA series Clock Generation Circuit
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compatible: "renesas,ra-clock-generation-circuit"
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include: [clock-controller.yaml, base.yaml]
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properties:
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reg:
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required: true
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iclk-div:
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type: int
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description: Division factor for ICLK
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fclk-div:
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type: int
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description: Division factor for FCLK
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pclka-div:
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type: int
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description: Division factor for PCLKA
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pclkb-div:
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type: int
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description: Division factor for PCLKB
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pclkc-div:
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type: int
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description: Division factor for PCLKC
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pclkd-div:
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type: int
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description: Division factor for PCLKD
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clock-source:
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type: phandle
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description: System clock source
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"#clock-cells":
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const: 1
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clock-cells:
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- id
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