373f8acaa7
The RISC-V FPU context switching code is intricate and sometimes subtle. Here's a test that exercizes various code paths to ensure they work as intended, and to confirm that the target hardware does behave as expected too. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
7 lines
118 B
Plaintext
7 lines
118 B
Plaintext
CONFIG_ZTEST=y
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CONFIG_ZTEST_NEW_API=y
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CONFIG_FPU=y
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CONFIG_FPU_SHARING=y
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CONFIG_IRQ_OFFLOAD=y
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CONFIG_MP_MAX_NUM_CPUS=1
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