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zephyr/drivers/clock_control/Kconfig.stm32
Erwan Gouriou 2bd15aa774 drivers: clock_control: stm32: Remove unsupported clock configuration 
In stm32 clock_control driver, Kconfig symbol CLOCK_STM32_PLL_PREDIV1
in stm32f3 series was set as conditional on the activation of some
specific STM32F3 SoCs that are not supported yet in Zephyr.
Remove this flag.
In order not to loose a rather studious part of code, comment it out
and set a TODO to specify how to re-enable it once it will be
required.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2018-05-24 08:04:00 -04:00

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# Kconfig - STM32 MCU clock control driver config
#
# Copyright (c) 2017 Linaro
# Copyright (c) 2017 RnDity Sp. z o.o.
#
# SPDX-License-Identifier: Apache-2.0
#
if SOC_FAMILY_STM32
menuconfig CLOCK_CONTROL_STM32_CUBE
bool
prompt "STM32 Reset & Clock Control"
depends on CLOCK_CONTROL
select USE_STM32_LL_UTILS
help
Enable driver for Reset & Clock Control subsystem found
in STM32 family of MCUs
if CLOCK_CONTROL_STM32_CUBE
config CLOCK_CONTROL_STM32_DEVICE_INIT_PRIORITY
int "Clock Control Device Priority"
default 1
help
This option controls the priority of clock control
device initialization. Higher priority ensures that the device
is initialized earlier in the startup cycle. If unsure, leave
at default value 1
choice CLOCK_STM32_SYSCLK_SRC
prompt "STM32 System Clock Source"
config CLOCK_STM32_SYSCLK_SRC_HSE
bool "HSE"
help
Use HSE as source of SYSCLK
config CLOCK_STM32_SYSCLK_SRC_HSI
bool "HSI"
help
Use HSI as source of SYSCLK
config CLOCK_STM32_SYSCLK_SRC_MSI
bool "MSI"
depends on SOC_SERIES_STM32L0X || SOC_SERIES_STM32L4X
help
Use MSI as source of SYSCLK
config CLOCK_STM32_SYSCLK_SRC_PLL
bool "PLL"
help
Use PLL as source of SYSCLK
endchoice #CLOCK_STM32_SYSCLK_SRC
config CLOCK_STM32_HSE_BYPASS
bool "HSE bypass"
depends on CLOCK_STM32_SYSCLK_SRC_HSE || CLOCK_STM32_PLL_SRC_HSE
default n
help
Enable this option to bypass external high-speed clock (HSE).
config CLOCK_STM32_HSE_CLOCK
int "HSE clock value"
depends on CLOCK_STM32_SYSCLK_SRC_HSE || CLOCK_STM32_PLL_SRC_HSE
default 8000000
help
Value of external high-speed clock (HSE).
choice
prompt "STM32 PLL Clock Source"
depends on CLOCK_STM32_SYSCLK_SRC_PLL
default CLOCK_STM32_PLL_SRC_HSI
config CLOCK_STM32_PLL_SRC_MSI
bool "MSI"
depends on SOC_SERIES_STM32L0X || SOC_SERIES_STM32L4X
help
Use MSI as source of PLL
config CLOCK_STM32_PLL_SRC_HSI
bool "HSI"
help
Use HSI as source of PLL
config CLOCK_STM32_PLL_SRC_HSE
bool "HSE"
help
Use HSE as source of PLL
config CLOCK_STM32_PLL_SRC_PLL2
bool "PLL2"
depends on SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE
help
Use PLL2 as source of main PLL. This is equivalent of defining
PLL2 as source PREDIV1SCR. If not selected, default source is HSE.
endchoice
if SOC_SERIES_STM32F0X
config CLOCK_STM32_PLL_PREDIV
int "PREDIV Prescaler"
default 1
range 1 16
help
PREDIV is PLLSCR clock signal prescaler, allowed values: 1 - 16.
config CLOCK_STM32_PLL_PREDIV1
int "PREDIV1 Prescaler"
depends on CLOCK_STM32_PLL_SRC_HSE
default 1
range 1 16
help
PREDIV is PLLSCR clock signal prescaler, present on STM32F0 SoC having
an HSE Oscillator available like the stm32f04xx, stm32f07xx,
stm32f09xx and stm32f030xc parts. If configured on a non supported
part, the HSI oscillator will be used a default PLL source and this
config will be ignored.
Allowed values: 1 - 16.
config CLOCK_STM32_PLL_MULTIPLIER
int "PLL multiplier"
depends on CLOCK_STM32_SYSCLK_SRC_PLL
default 6
range 2 16
help
PLL multiplier, allowed values: 2-16. PLL output must not exceed 48MHz.
endif # SOC_SERIES_STM32F0X
if SOC_SERIES_STM32F1X
config CLOCK_STM32_PLL_XTPRE
bool "HSE to PLL /2 prescaler"
depends on SOC_STM32F10X_DENSITY_DEVICE && CLOCK_STM32_PLL_SRC_HSE
help
Enable this option to enable /2 prescaler on HSE to PLL clock signal
config CLOCK_STM32_PLL_MULTIPLIER
int "PLL multiplier"
depends on CLOCK_STM32_SYSCLK_SRC_PLL
default 9
range 2 16 if SOC_STM32F10X_DENSITY_DEVICE
range 4 9 if SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE
help
PLL multiplier, PLL output must not exceed 72MHz. Allowed values:
Density devices: 2-16
Connectivity devices: 4 - 9 and 13 ( used for multiplication factor 6.5).
config CLOCK_STM32_PLL_PREDIV1
int "PREDIV1 Prescaler"
depends on SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE && CLOCK_STM32_SYSCLK_SRC_PLL
default 1
range 1 16
help
PREDIV1 is PLL clock signal prescaler, allowed values: 1 - 16.
config CLOCK_STM32_PLL2_MULTIPLIER
int "PLL2 multiplier"
depends on SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE && CLOCK_STM32_PLL_SRC_PLL2
default 8
range 8 20
help
PLL2 multiplier, allowed values: 8 - 20. 15-17-18-19 reserved
config CLOCK_STM32_PLL2_PREDIV2
int "PREDIV2 Prescaler"
depends on SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE && CLOCK_STM32_PLL_SRC_PLL2
default 1
range 1 16
help
PREDIV2 is PLL2 prescaler, allowed values: 1 - 16.
endif # SOC_SERIES_STM32F1X
if SOC_SERIES_STM32F3X
config CLOCK_STM32_PLL_PREDIV
int "PREDIV Prescaler"
default 1
range 1 16
help
PREDIV is PLLSCR clock signal prescaler, allowed values: 1 - 16.
config CLOCK_STM32_PLL_MULTIPLIER
int "PLL multiplier"
depends on CLOCK_STM32_SYSCLK_SRC_PLL
default 9
range 2 16
help
PLL multiplier, allowed values: 2-16. PLL output must not exceed 72MHz.
endif # SOC_SERIES_STM32F3X
if SOC_SERIES_STM32F4X
config CLOCK_STM32_PLL_M_DIVISOR
int "Division factor for PLL VCO input clock"
depends on CLOCK_STM32_SYSCLK_SRC_PLL
default 8
range 2 63
help
PLLM division factor needs to be set correctly to ensure that the VCO
input frequency ranges from 1 to 2 MHz. It is recommended to select a
frequency of 2 MHz to limit PLL jitter.
Allowed values: 2-63
config CLOCK_STM32_PLL_N_MULTIPLIER
int "Multiplier factor for PLL VCO output clock"
depends on CLOCK_STM32_SYSCLK_SRC_PLL
default 336
range 192 432 if SOC_STM32F401XE
range 50 432
help
PLLN multiplier factor needs to be set correctly to ensure that the
VCO output frequency is between 100 and 432 MHz, except on STM32F401
where the frequency must be between 192 and 432 MHz.
Allowed values: 50-432 (STM32F401: 192-432)
config CLOCK_STM32_PLL_P_DIVISOR
int "PLL division factor for main system clock"
depends on CLOCK_STM32_SYSCLK_SRC_PLL
default 4
range 2 8
help
PLLP division factor needs to be set correctly to not exceed 84MHz.
Allowed values: 2, 4, 6, 8
config CLOCK_STM32_PLL_Q_DIVISOR
int "Division factor for OTG FS, SDIO and RNG clocks"
depends on CLOCK_STM32_SYSCLK_SRC_PLL
default 7
range 2 15
help
The USB OTG FS requires a 48MHz clock to work correctly. SDIO and RNG
need a frequency lower than or equal to 48 MHz to work correctly.
Allowed values: 2-15
endif # SOC_SERIES_STM32F4X
if SOC_SERIES_STM32L0X
config CLOCK_STM32_PLL_MULTIPLIER
int "PLL multiplier"
depends on CLOCK_STM32_SYSCLK_SRC_PLL
default 4
range 3 48
help
PLL multiplier, allowed values: 3, 4, 6, 8, 12, 16, 24, 32, 48.
PLL output must not exceed 96MHz(1.8V)/48MHz(1.5V)/24MHz(1.2V).
config CLOCK_STM32_PLL_DIVISOR
int "PLL divisor"
depends on CLOCK_STM32_SYSCLK_SRC_PLL
default 2
range 2 4
help
PLL divisor, allowed values: 2-4.
endif # SOC_SERIES_STM32L0X
if SOC_SERIES_STM32L4X
config CLOCK_STM32_PLL_M_DIVISOR
int "PLL divisor"
depends on CLOCK_STM32_SYSCLK_SRC_PLL
default 1
range 1 8
help
PLL divisor, allowed values: 1-8. With this ensure that the PLL
VCO input frequency ranges from 4 to 16MHz.
config CLOCK_STM32_PLL_N_MULTIPLIER
int "PLL multiplier"
depends on CLOCK_STM32_SYSCLK_SRC_PLL
default 20
range 8 86
help
PLL multiplier, allowed values: 2-16. PLL output must not
exceed 344MHz.
config CLOCK_STM32_PLL_P_DIVISOR
int "PLL P Divisor"
depends on CLOCK_STM32_SYSCLK_SRC_PLL
default 7
range 0 17
help
PLL P Output divisor, allowed values: 0, 7, 17.
config CLOCK_STM32_PLL_Q_DIVISOR
int "PLL Q Divisor"
depends on CLOCK_STM32_SYSCLK_SRC_PLL
default 2
range 0 8
help
PLL Q Output divisor, allowed values: 0, 2, 4, 6, 8.
config CLOCK_STM32_PLL_R_DIVISOR
int "PLL R Divisor"
depends on CLOCK_STM32_SYSCLK_SRC_PLL
default 4
range 0 8
help
PLL R Output divisor, allowed values: 0, 2, 4, 6, 8.
endif # SOC_SERIES_STM32L4X
config CLOCK_STM32_AHB_PRESCALER
int "AHB prescaler"
default 0
range 0 512
help
AHB prescaler, allowed values: 1, 2, 4, 8, 16, 64, 128,
256, 512.
config CLOCK_STM32_APB1_PRESCALER
int "APB1 prescaler"
default 1
range 1 16
help
APB1 Low speed clock (PCLK1) prescaler, allowed values:
1, 2, 4, 8, 16
if SOC_SERIES_STM32F0X!=y
config CLOCK_STM32_APB2_PRESCALER
int "APB2 prescaler"
default 1
range 1 16
help
APB2 High speed clock (PCLK2) prescaler, allowed values:
1, 2, 4, 8, 16
endif # SOC_SERIES_STM32F0X!=y
endif # CLOCK_CONTROL_STM32_CUBE
endif # SOC_FAMILY_STM32
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