2c5ca5505c
The current AArch32 (Cortex-R and to-be-added Cortex-A) interrupt system relies on the multi-level interrupt mechanism and the `irq_nextlevel` public interface to invoke the Generic Interrupt Controller (GIC) driver functions. Since the GIC driver has been refactored to provide a direct interface, in order to resolve various implementation issues described in the GIC driver refactoring commit, the architecture interrupt control functions are updated to directly invoke the GIC driver functions. This commit also adds support for the Cortex-R cores (Cortex-R4 and R5) that allow interfacing to a custom external interrupt controller (i.e. non-GIC) by introducing the `ARM_CUSTOM_INTERRUPT_CONTROLLER` configuration that maps the architecture interrupt control functions to the SoC layer interrupt control functions. Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
40 lines
1.1 KiB
Plaintext
40 lines
1.1 KiB
Plaintext
# ARM architecture configuration options
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# Copyright (c) 2014-2015 Wind River Systems, Inc.
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# SPDX-License-Identifier: Apache-2.0
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menu "ARM Options"
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depends on ARM
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rsource "core/aarch32/Kconfig"
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rsource "core/aarch64/Kconfig"
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config ARCH
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default "arm"
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config ARM64
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bool
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select 64BIT
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config ARM_CUSTOM_INTERRUPT_CONTROLLER
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bool
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depends on !CPU_CORTEX_M
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help
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This option indicates that the ARM CPU is connected to a custom (i.e.
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non-GIC) interrupt controller.
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A number of Cortex-A and Cortex-R cores (Cortex-A5, Cortex-R4/5, ...)
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allow interfacing to a custom external interrupt controller and this
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option must be selected when such cores are connected to an interrupt
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controller that is not the ARM Generic Interrupt Controller (GIC).
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When this option is selected, the architecture interrupt control
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functions are mapped to the SoC interrupt control interface, which is
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implemented at the SoC level.
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N.B. This option is only applicable to the Cortex-A and Cortex-R
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family cores. The Cortex-M family cores are always equipped with
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the ARM Nested Vectored Interrupt Controller (NVIC).
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endmenu
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