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zephyr/arch
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Daniel Leung e444cc9fb9 xtensa: mmu: always map data TLB for VECBASE 
This adds code to always map data TLB for VECBASE so that
we would be dealing with fewer data TLB misses during
exception handling. With VECBASE always mapped, there is
no need to pre-load anymore.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2023-05-23 08:54:29 +02:00
..
arc ARC: tweak _st32_huge_offset macro to have same behaviour with GNU & MWDT 2023-05-04 22:50:14 +09:00
arm arch: arm: aarch32: Remove CPU type dependency from CONFIG_FP16 2023-05-22 10:17:02 +02:00
arm64 arm64: cache: Enable full inlining of the cache ops 2023-04-20 14:56:09 -04:00
common revert: "linker: rom_start_offset: add to address" 2023-03-30 18:19:32 -04:00
mips include: types: remove ulong_t 2022-09-06 18:16:33 +02:00
nios2 arch: nios2: Remove unused absolute symbols 2023-04-18 10:51:28 -04:00
posix arch posix: posix_cheats.h main() type changed in comment 2023-04-14 09:55:48 +02:00
riscv arch: riscv: add ARCH_HAS_SINGLE_THREAD_SUPPORT 2023-05-12 09:56:40 +02:00
sparc arch: sparc: Remove unused absolute symbols 2023-04-18 10:51:28 -04:00
x86 arch: x86: add irq runtime statistics 2023-05-22 13:29:14 -04:00
xtensa xtensa: mmu: always map data TLB for VECBASE 2023-05-23 08:54:29 +02:00
CMakeLists.txt cmake: fix include directories to work with out-of-tree arch 2020-08-05 08:06:07 -04:00
Kconfig arch: riscv enable flash config 2023-02-28 10:29:03 +01:00