37c13eec7a
RCC device could be common to various STM32 series. Until now, PLL handling code was set in series specific files, even if it was driving the same device than another series. Minimize code duplication by factorizing code between series when possible. With this change, some series get additional features by getting access to code developed for other series. Additionally, while renaming the files, remove the non informative 'x' to minimize file name length Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
90 lines
2.2 KiB
C
90 lines
2.2 KiB
C
/*
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*
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* Copyright (c) 2017 Linaro Limited.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <soc.h>
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#include <clock_control.h>
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#include <misc/util.h>
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#include <clock_control/stm32_clock_control.h>
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#include "clock_stm32_ll_common.h"
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#ifdef CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL
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/**
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* @brief fill in pll configuration structure
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*/
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void config_pll_init(LL_UTILS_PLLInitTypeDef *pllinit)
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{
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/*
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* PLL MUL
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* 2 -> LL_RCC_PLL_MUL_2 -> 0x00000000
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* 3 -> LL_RCC_PLL_MUL_3 -> 0x00040000
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* 4 -> LL_RCC_PLL_MUL_4 -> 0x00080000
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* ...
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* 16 -> LL_RCC_PLL_MUL_16 -> 0x00380000
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*/
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pllinit->PLLMul = ((CONFIG_CLOCK_STM32_PLL_MULTIPLIER - 2)
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<< RCC_CFGR_PLLMUL_Pos);
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#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
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/* PREDIV support is a specific RCC configuration present on */
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/* following SoCs: STM32F070x6, STM32F070xB and STM32F030xC */
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/* cf Reference manual for more details */
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#if defined(CONFIG_CLOCK_STM32_PLL_SRC_HSI)
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pllinit->PLLDiv = LL_RCC_PLLSOURCE_HSI;
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#else
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#if defined(CONFIG_CLOCK_STM32_PLL_PREDIV1)
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/*
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* PLL DIV
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* 1 -> LL_RCC_PLLSOURCE_HSE_DIV_1 -> 0x00010000
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* 2 -> LL_RCC_PLLSOURCE_HSE_DIV_2 -> 0x00010001
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* 3 -> LL_RCC_PLLSOURCE_HSE_DIV_3 -> 0x00010002
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* ...
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* 16 -> LL_RCC_PLLSOURCE_HSE_DIV_16 -> 0x0001000F
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*/
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pllinit->PLLDiv = (RCC_CFGR_PLLSRC_HSE_PREDIV |
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(CONFIG_CLOCK_STM32_PLL_PREDIV1 - 1));
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#endif /* CONFIG_CLOCK_STM32_PLL_PREDIV1 */
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#endif /* CONFIG_CLOCK_STM32_PLL_SRC_HSI */
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#else
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/*
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* PLL Prediv
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* 1 -> LL_RCC_PREDIV_DIV_1 -> 0x00000000
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* 2 -> LL_RCC_PREDIV_DIV_2 -> 0x00000001
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* 3 -> LL_RCC_PREDIV_DIV_3 -> 0x00000002
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* ...
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* 16 -> LL_RCC_PREDIV_DIV_16 -> 0x0000000F
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*/
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pllinit->Prediv = CONFIG_CLOCK_STM32_PLL_PREDIV - 1;
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#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
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}
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#endif /* CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL */
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/**
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* @brief Activate default clocks
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*/
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void config_enable_default_clocks(void)
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{
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#ifndef CONFIG_SOC_SERIES_STM32F3X
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#if defined(CONFIG_EXTI_STM32) || defined(CONFIG_USB_DC_STM32)
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/* Enable System Configuration Controller clock. */
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LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_SYSCFG);
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#endif
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#endif /* !CONFIG_SOC_SERIES_STM32F3X */
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}
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/**
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* @brief Function kept for driver genericity
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*/
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void LL_RCC_MSI_Disable(void)
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{
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/* Do nothing */
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}
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