Joshua Lilly cce530cae4 scripts: build: gen_isr_tables: make bit masks configurable ... Some architectures such as RISC-v support more than 255 interrupts per aggrigator. This diff adds the ability to forgo the aggrigator pattern and use a configurable number of bits for multilevel interruts. Signed-off-by: Joshua Lilly <jgl@meta.com>		2023-08-10 10:55:41 -04:00
..
data_structures	doc: Fix kernel data structures typos	2022-10-10 21:01:51 -04:00
drivers	fix: doc: in kernel/drivers interrupts function had mismatching types	2023-02-22 16:58:29 -05:00
iterable_sections	doc: move misc services into OS Service section	2022-04-07 16:35:19 +02:00
memory_management	doc: kernel: Re-organise memory management API pages	2022-06-01 15:26:48 +02:00
services	scripts: build: gen_isr_tables: make bit masks configurable	2023-08-10 10:55:41 -04:00
timing_functions	include: update documentation to use zephyr/ prefix	2022-04-21 07:40:54 -05:00
usermode	doc: kernel/syscalls: about limiting syscalls in binaries	2023-06-17 07:57:45 -04:00
util	doc: move utility functions to kernel	2022-04-07 16:35:19 +02:00
code-relocation.rst	doc: kernel: code-relocation: Remove erroneous note	2023-07-10 10:01:42 +00:00
index.rst	doc: develop: Add 'Language Support' sub-category	2022-06-01 15:26:48 +02:00
timeutil.rst	doc: move timeutil to kernel	2022-04-07 16:35:19 +02:00