a0df4272ac
Squash the two copies of this file found in `dts/arm` and `dts/arm64`. Their contents were identical up to devicetree property ordering. Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
66 lines
1.3 KiB
Plaintext
66 lines
1.3 KiB
Plaintext
/*
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* Copyright 2020 Broadcom
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm64/armv8-a.dtsi>
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#include <broadcom/viper-common.dtsi>
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#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a72";
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reg = <0>;
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>;
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};
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soc {
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gic: interrupt-controller@42700000 {
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compatible = "arm,gic-v3", "arm,gic";
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reg = <0x42700000 0x010000>,
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<0x42780000 0x600000>;
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interrupt-controller;
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#interrupt-cells = <4>;
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status = "okay";
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};
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};
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};
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&uart0 {
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>;
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};
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&uart1 {
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>;
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};
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&paxdma {
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>;
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};
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