0369998e61
MIPS (Microprocessor without Interlocked Pipelined Stages) is a instruction set architecture (ISA) developed by MIPS Computer Systems, now MIPS Technologies. This commit provides MIPS architecture support to Zephyr. It is compatible with the MIPS32 Release 1 specification. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
17 lines
234 B
CMake
17 lines
234 B
CMake
# SPDX-License-Identifier: Apache-2.0
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zephyr_library()
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zephyr_library_sources(
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cpu_idle.c
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fatal.c
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irq_manage.c
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isr.S
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prep_c.c
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reset.S
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swap.S
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thread.c
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)
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zephyr_library_sources_ifdef(CONFIG_IRQ_OFFLOAD irq_offload.c)
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