790794ce84
The typical number of needed translation tables depends on memory domain usage and userspace support, but also on the virtual address space width due to the number of translation levels involved. Reflect that in the default value. Also fix a related comment where values were off by 1. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
96 lines
3 KiB
C
96 lines
3 KiB
C
/*
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* Copyright 2019 Broadcom
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* The term "Broadcom" refers to Broadcom Inc. and/or its subsidiaries.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* Set below flag to get debug prints */
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#define MMU_DEBUG_PRINTS 0
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#if MMU_DEBUG_PRINTS
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/* To dump page table entries while filling them, set DUMP_PTE macro */
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#define DUMP_PTE 0
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#define MMU_DEBUG(fmt, ...) printk(fmt, ##__VA_ARGS__)
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#else
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#define MMU_DEBUG(...)
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#endif
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/*
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* 48-bit address with 4KB granule size:
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*
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* +------------+------------+------------+------------+-----------+
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* | VA [47:39] | VA [38:30] | VA [29:21] | VA [20:12] | VA [11:0] |
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* +---------------------------------------------------------------+
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* | L0 | L1 | L2 | L3 | block off |
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* +------------+------------+------------+------------+-----------+
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*/
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/* Only 4K granule is supported */
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#define PAGE_SIZE_SHIFT 12U
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/* 48-bit VA address */
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#define VA_SIZE_SHIFT_MAX 48U
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/* Maximum 4 XLAT table levels (L0 - L3) */
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#define XLAT_LAST_LEVEL 3U
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/* The VA shift of L3 depends on the granule size */
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#define L3_XLAT_VA_SIZE_SHIFT PAGE_SIZE_SHIFT
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/* Number of VA bits to assign to each table (9 bits) */
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#define Ln_XLAT_VA_SIZE_SHIFT (PAGE_SIZE_SHIFT - 3)
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/* Starting bit in the VA address for each level */
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#define L2_XLAT_VA_SIZE_SHIFT (L3_XLAT_VA_SIZE_SHIFT + Ln_XLAT_VA_SIZE_SHIFT)
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#define L1_XLAT_VA_SIZE_SHIFT (L2_XLAT_VA_SIZE_SHIFT + Ln_XLAT_VA_SIZE_SHIFT)
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#define L0_XLAT_VA_SIZE_SHIFT (L1_XLAT_VA_SIZE_SHIFT + Ln_XLAT_VA_SIZE_SHIFT)
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#define LEVEL_TO_VA_SIZE_SHIFT(level) \
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(PAGE_SIZE_SHIFT + (Ln_XLAT_VA_SIZE_SHIFT * \
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(XLAT_LAST_LEVEL - (level))))
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/* Number of entries for each table (512) */
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#define Ln_XLAT_NUM_ENTRIES ((1U << PAGE_SIZE_SHIFT) / 8U)
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/* Virtual Address Index within a given translation table level */
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#define XLAT_TABLE_VA_IDX(va_addr, level) \
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((va_addr >> LEVEL_TO_VA_SIZE_SHIFT(level)) & (Ln_XLAT_NUM_ENTRIES - 1))
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/*
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* Calculate the initial translation table level from CONFIG_ARM64_VA_BITS
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* For a 4 KB page size:
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*
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* (va_bits <= 21) - base level 3
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* (22 <= va_bits <= 30) - base level 2
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* (31 <= va_bits <= 39) - base level 1
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* (40 <= va_bits <= 48) - base level 0
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*/
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#define GET_BASE_XLAT_LEVEL(va_bits) \
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((va_bits > L0_XLAT_VA_SIZE_SHIFT) ? 0U \
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: (va_bits > L1_XLAT_VA_SIZE_SHIFT) ? 1U \
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: (va_bits > L2_XLAT_VA_SIZE_SHIFT) ? 2U : 3U)
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/* Level for the base XLAT */
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#define BASE_XLAT_LEVEL GET_BASE_XLAT_LEVEL(CONFIG_ARM64_VA_BITS)
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#if (CONFIG_ARM64_PA_BITS == 48)
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#define TCR_PS_BITS TCR_PS_BITS_256TB
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#elif (CONFIG_ARM64_PA_BITS == 44)
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#define TCR_PS_BITS TCR_PS_BITS_16TB
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#elif (CONFIG_ARM64_PA_BITS == 42)
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#define TCR_PS_BITS TCR_PS_BITS_4TB
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#elif (CONFIG_ARM64_PA_BITS == 40)
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#define TCR_PS_BITS TCR_PS_BITS_1TB
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#elif (CONFIG_ARM64_PA_BITS == 36)
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#define TCR_PS_BITS TCR_PS_BITS_64GB
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#else
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#define TCR_PS_BITS TCR_PS_BITS_4GB
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#endif
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/* Upper and lower attributes mask for page/block descriptor */
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#define DESC_ATTRS_UPPER_MASK GENMASK(63, 51)
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#define DESC_ATTRS_LOWER_MASK GENMASK(11, 2)
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#define DESC_ATTRS_MASK (DESC_ATTRS_UPPER_MASK | DESC_ATTRS_LOWER_MASK)
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