4a8d9a1ef3
Add ENET clock value to the CCM clock decoder for both RT10XX and RT11XX CCM versions. Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
339 lines
7.6 KiB
C
339 lines
7.6 KiB
C
/*
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* Copyright (c) 2017, NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT nxp_imx_ccm
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#include <errno.h>
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#include <zephyr/arch/cpu.h>
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#include <zephyr/sys/util.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/dt-bindings/clock/imx_ccm.h>
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#include <fsl_clock.h>
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#if defined(CONFIG_SOC_MIMX8QM_ADSP) || defined(CONFIG_SOC_MIMX8QXP_ADSP)
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#include <main/ipc.h>
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#endif
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#define LOG_LEVEL CONFIG_CLOCK_CONTROL_LOG_LEVEL
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(clock_control);
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#ifdef CONFIG_SPI_MCUX_LPSPI
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static const clock_name_t lpspi_clocks[] = {
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kCLOCK_Usb1PllPfd1Clk,
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kCLOCK_Usb1PllPfd0Clk,
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kCLOCK_SysPllClk,
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kCLOCK_SysPllPfd2Clk,
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};
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#endif
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#ifdef CONFIG_UART_MCUX_IUART
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static const clock_root_control_t uart_clk_root[] = {
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kCLOCK_RootUart1,
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kCLOCK_RootUart2,
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kCLOCK_RootUart3,
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kCLOCK_RootUart4,
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};
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static const clock_ip_name_t uart_clocks[] = {
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kCLOCK_Uart1,
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kCLOCK_Uart2,
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kCLOCK_Uart3,
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kCLOCK_Uart4,
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};
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#endif
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#ifdef CONFIG_UART_MCUX_LPUART
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#ifdef CONFIG_SOC_MIMX8QM_ADSP
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static const clock_ip_name_t lpuart_clocks[] = {
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kCLOCK_DMA_Lpuart0,
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kCLOCK_DMA_Lpuart1,
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kCLOCK_DMA_Lpuart2,
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kCLOCK_DMA_Lpuart3,
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kCLOCK_DMA_Lpuart4,
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};
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static const uint32_t lpuart_rate = MHZ(80);
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#endif /* CONFIG_SOC_MIMX8QM_ADSP */
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#ifdef CONFIG_SOC_MIMX8QXP_ADSP
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static const clock_ip_name_t lpuart_clocks[] = {
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kCLOCK_DMA_Lpuart0,
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kCLOCK_DMA_Lpuart1,
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kCLOCK_DMA_Lpuart2,
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kCLOCK_DMA_Lpuart3,
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};
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static const uint32_t lpuart_rate = MHZ(80);
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#endif /* CONFIG_SOC_MIMX8QXP_ADSP */
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#endif /* CONFIG_UART_MCUX_LPUART */
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static int mcux_ccm_on(const struct device *dev,
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clock_control_subsys_t sub_system)
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{
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uint32_t clock_name = (uintptr_t)sub_system;
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uint32_t instance = clock_name & IMX_CCM_INSTANCE_MASK;
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switch (clock_name) {
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#ifdef CONFIG_UART_MCUX_IUART
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case IMX_CCM_UART1_CLK:
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case IMX_CCM_UART2_CLK:
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case IMX_CCM_UART3_CLK:
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case IMX_CCM_UART4_CLK:
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CLOCK_EnableClock(uart_clocks[instance]);
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return 0;
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#endif
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#if defined(CONFIG_UART_MCUX_LPUART) && defined(CONFIG_SOC_MIMX8QM_ADSP)
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case IMX_CCM_LPUART1_CLK:
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case IMX_CCM_LPUART2_CLK:
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case IMX_CCM_LPUART3_CLK:
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case IMX_CCM_LPUART4_CLK:
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case IMX_CCM_LPUART5_CLK:
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CLOCK_EnableClock(lpuart_clocks[instance]);
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return 0;
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#endif
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#if defined(CONFIG_UART_MCUX_LPUART) && defined(CONFIG_SOC_MIMX8QXP_ADSP)
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case IMX_CCM_LPUART1_CLK:
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case IMX_CCM_LPUART2_CLK:
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case IMX_CCM_LPUART3_CLK:
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case IMX_CCM_LPUART4_CLK:
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CLOCK_EnableClock(lpuart_clocks[instance]);
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return 0;
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#endif
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default:
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(void)instance;
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return 0;
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}
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}
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static int mcux_ccm_off(const struct device *dev,
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clock_control_subsys_t sub_system)
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{
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uint32_t clock_name = (uintptr_t)sub_system;
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uint32_t instance = clock_name & IMX_CCM_INSTANCE_MASK;
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switch (clock_name) {
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#ifdef CONFIG_UART_MCUX_IUART
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case IMX_CCM_UART1_CLK:
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case IMX_CCM_UART2_CLK:
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case IMX_CCM_UART3_CLK:
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case IMX_CCM_UART4_CLK:
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CLOCK_DisableClock(uart_clocks[instance]);
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return 0;
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#endif
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default:
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(void)instance;
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return 0;
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}
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}
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static int mcux_ccm_get_subsys_rate(const struct device *dev,
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clock_control_subsys_t sub_system,
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uint32_t *rate)
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{
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uint32_t clock_name = (uintptr_t)sub_system;
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switch (clock_name) {
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#ifdef CONFIG_I2C_MCUX_LPI2C
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case IMX_CCM_LPI2C_CLK:
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if (CLOCK_GetMux(kCLOCK_Lpi2cMux) == 0) {
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*rate = CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 8
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/ (CLOCK_GetDiv(kCLOCK_Lpi2cDiv) + 1);
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} else {
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*rate = CLOCK_GetOscFreq()
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/ (CLOCK_GetDiv(kCLOCK_Lpi2cDiv) + 1);
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}
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break;
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#endif
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#ifdef CONFIG_SPI_MCUX_LPSPI
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case IMX_CCM_LPSPI_CLK:
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{
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uint32_t lpspi_mux = CLOCK_GetMux(kCLOCK_LpspiMux);
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clock_name_t lpspi_clock = lpspi_clocks[lpspi_mux];
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*rate = CLOCK_GetFreq(lpspi_clock)
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/ (CLOCK_GetDiv(kCLOCK_LpspiDiv) + 1);
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break;
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}
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#endif
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#ifdef CONFIG_UART_MCUX_LPUART
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#if defined(CONFIG_SOC_MIMX8QM_ADSP)
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case IMX_CCM_LPUART1_CLK:
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case IMX_CCM_LPUART2_CLK:
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case IMX_CCM_LPUART3_CLK:
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case IMX_CCM_LPUART4_CLK:
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case IMX_CCM_LPUART5_CLK:
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uint32_t instance = clock_name & IMX_CCM_INSTANCE_MASK;
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CLOCK_SetIpFreq(lpuart_clocks[instance], lpuart_rate);
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*rate = CLOCK_GetIpFreq(lpuart_clocks[instance]);
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break;
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#elif defined(CONFIG_SOC_MIMX8QXP_ADSP)
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case IMX_CCM_LPUART1_CLK:
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case IMX_CCM_LPUART2_CLK:
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case IMX_CCM_LPUART3_CLK:
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case IMX_CCM_LPUART4_CLK:
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uint32_t instance = clock_name & IMX_CCM_INSTANCE_MASK;
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CLOCK_SetIpFreq(lpuart_clocks[instance], lpuart_rate);
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*rate = CLOCK_GetIpFreq(lpuart_clocks[instance]);
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break;
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#else
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case IMX_CCM_LPUART_CLK:
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if (CLOCK_GetMux(kCLOCK_UartMux) == 0) {
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*rate = CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6
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/ (CLOCK_GetDiv(kCLOCK_UartDiv) + 1);
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} else {
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*rate = CLOCK_GetOscFreq()
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/ (CLOCK_GetDiv(kCLOCK_UartDiv) + 1);
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}
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break;
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#endif
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) && CONFIG_IMX_USDHC
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case IMX_CCM_USDHC1_CLK:
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*rate = CLOCK_GetSysPfdFreq(kCLOCK_Pfd0) /
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(CLOCK_GetDiv(kCLOCK_Usdhc1Div) + 1U);
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break;
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc2), okay) && CONFIG_IMX_USDHC
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case IMX_CCM_USDHC2_CLK:
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*rate = CLOCK_GetSysPfdFreq(kCLOCK_Pfd0) /
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(CLOCK_GetDiv(kCLOCK_Usdhc2Div) + 1U);
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break;
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#endif
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#ifdef CONFIG_DMA_MCUX_EDMA
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case IMX_CCM_EDMA_CLK:
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*rate = CLOCK_GetIpgFreq();
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break;
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#endif
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#ifdef CONFIG_PWM_MCUX
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case IMX_CCM_PWM_CLK:
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*rate = CLOCK_GetIpgFreq();
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break;
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#endif
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#ifdef CONFIG_ETH_NXP_ENET
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case IMX_CCM_ENET_CLK:
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*rate = CLOCK_GetIpgFreq();
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break;
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#endif
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#ifdef CONFIG_UART_MCUX_IUART
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case IMX_CCM_UART1_CLK:
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case IMX_CCM_UART2_CLK:
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case IMX_CCM_UART3_CLK:
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case IMX_CCM_UART4_CLK:
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{
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uint32_t instance = clock_name & IMX_CCM_INSTANCE_MASK;
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clock_root_control_t clk_root = uart_clk_root[instance];
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uint32_t uart_mux = CLOCK_GetRootMux(clk_root);
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if (uart_mux == 0) {
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*rate = MHZ(24);
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} else if (uart_mux == 1) {
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*rate = CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) /
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(CLOCK_GetRootPreDivider(clk_root)) /
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(CLOCK_GetRootPostDivider(clk_root)) /
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10;
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}
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} break;
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#endif
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#ifdef CONFIG_CAN_MCUX_FLEXCAN
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case IMX_CCM_CAN_CLK:
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{
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uint32_t can_mux = CLOCK_GetMux(kCLOCK_CanMux);
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if (can_mux == 0) {
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*rate = CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 8
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/ (CLOCK_GetDiv(kCLOCK_CanDiv) + 1);
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} else if (can_mux == 1) {
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*rate = CLOCK_GetOscFreq()
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/ (CLOCK_GetDiv(kCLOCK_CanDiv) + 1);
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} else {
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*rate = CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6
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/ (CLOCK_GetDiv(kCLOCK_CanDiv) + 1);
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}
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} break;
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#endif
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#ifdef CONFIG_COUNTER_MCUX_GPT
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case IMX_CCM_GPT_CLK:
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*rate = CLOCK_GetFreq(kCLOCK_PerClk);
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break;
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#endif
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#ifdef CONFIG_COUNTER_MCUX_QTMR
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case IMX_CCM_QTMR_CLK:
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*rate = CLOCK_GetIpgFreq();
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break;
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#endif
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#ifdef CONFIG_I2S_MCUX_SAI
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case IMX_CCM_SAI1_CLK:
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*rate = CLOCK_GetFreq(kCLOCK_AudioPllClk)
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/ (CLOCK_GetDiv(kCLOCK_Sai1PreDiv) + 1)
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/ (CLOCK_GetDiv(kCLOCK_Sai1Div) + 1);
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break;
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case IMX_CCM_SAI2_CLK:
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*rate = CLOCK_GetFreq(kCLOCK_AudioPllClk)
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/ (CLOCK_GetDiv(kCLOCK_Sai2PreDiv) + 1)
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/ (CLOCK_GetDiv(kCLOCK_Sai2Div) + 1);
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break;
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case IMX_CCM_SAI3_CLK:
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*rate = CLOCK_GetFreq(kCLOCK_AudioPllClk)
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/ (CLOCK_GetDiv(kCLOCK_Sai3PreDiv) + 1)
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/ (CLOCK_GetDiv(kCLOCK_Sai3Div) + 1);
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break;
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#endif
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}
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return 0;
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}
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static const struct clock_control_driver_api mcux_ccm_driver_api = {
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.on = mcux_ccm_on,
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.off = mcux_ccm_off,
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.get_rate = mcux_ccm_get_subsys_rate,
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};
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static int mcux_ccm_init(const struct device *dev)
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{
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#if defined(CONFIG_SOC_MIMX8QM_ADSP) || defined(CONFIG_SOC_MIMX8QXP_ADSP)
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sc_ipc_t ipc_handle;
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int ret;
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ret = sc_ipc_open(&ipc_handle, DT_REG_ADDR(DT_NODELABEL(scu_mu)));
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if (ret != SC_ERR_NONE) {
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return -ENODEV;
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}
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CLOCK_Init(ipc_handle);
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#endif
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return 0;
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}
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DEVICE_DT_INST_DEFINE(0, mcux_ccm_init, NULL, NULL, NULL,
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PRE_KERNEL_1, CONFIG_CLOCK_CONTROL_INIT_PRIORITY,
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&mcux_ccm_driver_api);
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