f426ad16e1
The description is a bit misleading as the packet is not even read in the mentioned case by the OA TC6 Zephyr driver. When the timeout occurs the data (packet) received by LAN865x may be: - Read latter if still in the RX buffer of LAN865x or - Is (probably) dropped by LAN8651 itself as the RX buffer gets overrun Signed-off-by: Lukasz Majewski <lukma@denx.de>
52 lines
1.4 KiB
Plaintext
52 lines
1.4 KiB
Plaintext
# Copyright (c) 2023 DENX Software Engineering GmbH
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# SPDX-License-Identifier: Apache-2.0
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menuconfig ETH_LAN865X
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bool "LAN865X 10BASE-T1S Controller"
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default y
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depends on DT_HAS_MICROCHIP_LAN865X_ENABLED
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select SPI
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select NET_L2_ETHERNET_MGMT
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help
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The LAN865X is a low power, 10BASE-T1S transceiver compliant with
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the IEEE® 802.3cg-2019™ Ethernet standard for long reach, 10
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Mbps single pair Ethernet (SPE).
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Featuring an integrated media access control (MAC) and a PHY,
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the LAN865X enables direct connectivity with a variety of controllers
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via a serial peripheral inter-face (SPI).
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if ETH_LAN865X
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config ETH_LAN865X_INIT_PRIORITY
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int "LAN865X driver init priority"
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default 72
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help
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LAN865X device driver initialization priority.
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Must be initialized after SPI.
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config ETH_LAN865X_IRQ_THREAD_STACK_SIZE
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int "Stack size for a thread that processes IRQ"
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default 512
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help
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Size of the stack used for internal thread which is ran to
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process raised INT IRQ.
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config ETH_LAN865X_IRQ_THREAD_PRIO
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int "Priority for internal incoming packet handler"
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default 2
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help
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Priority level for internal thread which is ran for LAN
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INT IRQ processing.
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config ETH_LAN865X_TIMEOUT
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int "IP buffer timeout"
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default 100
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help
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Given timeout in milliseconds. Maximum amount of time
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that the driver will wait from the IP stack to get
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a memory buffer.
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endif # ETH_LAN865X
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