2168d80987
This patch adds basic support for the PWM devices available on the Atmel SAM family. Beside enabling the driver, everything is selected through the device tree, including enabling the PWM0 and PWM1 devices. Thus CONFIG_PWM_0 and CONFIG_PWM_1 are ignored. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
120 lines
2.9 KiB
C
120 lines
2.9 KiB
C
/*
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* Copyright (c) 2019 Aurelien Jarno
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <device.h>
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#include <errno.h>
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#include <pwm.h>
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#include <soc.h>
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#define LOG_LEVEL CONFIG_PWM_LOG_LEVEL
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#include <logging/log.h>
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LOG_MODULE_REGISTER(pwm_sam);
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struct sam_pwm_config {
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Pwm *regs;
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u32_t id;
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u8_t prescaler;
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u8_t divider;
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};
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#define DEV_CFG(dev) \
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((const struct sam_pwm_config * const)(dev)->config->config_info)
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static int sam_pwm_get_cycles_per_sec(struct device *dev, u32_t pwm,
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u64_t *cycles)
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{
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u8_t prescaler = DEV_CFG(dev)->prescaler;
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u8_t divider = DEV_CFG(dev)->divider;
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*cycles = SOC_ATMEL_SAM_MCK_FREQ_HZ /
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((1 << prescaler) * divider);
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return 0;
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}
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static int sam_pwm_pin_set(struct device *dev, u32_t ch,
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u32_t period_cycles, u32_t pulse_cycles)
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{
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Pwm *const pwm = DEV_CFG(dev)->regs;
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if (ch >= PWMCHNUM_NUMBER) {
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return -EINVAL;
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}
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if (period_cycles == 0 || pulse_cycles > period_cycles) {
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return -EINVAL;
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}
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if (period_cycles > 0xffff) {
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return -ENOTSUP;
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}
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/* Select clock A */
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pwm->PWM_CH_NUM[ch].PWM_CMR = PWM_CMR_CPRE_CLKA_Val;
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/* Update period and pulse using the update registers, so that the
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* change is triggered at the next PWM period.
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*/
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pwm->PWM_CH_NUM[ch].PWM_CPRDUPD = period_cycles;
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pwm->PWM_CH_NUM[ch].PWM_CDTYUPD = pulse_cycles;
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/* Enable the output */
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pwm->PWM_ENA = 1 << ch;
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return 0;
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}
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static int sam_pwm_init(struct device *dev)
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{
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Pwm *const pwm = DEV_CFG(dev)->regs;
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u32_t id = DEV_CFG(dev)->id;
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u8_t prescaler = DEV_CFG(dev)->prescaler;
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u8_t divider = DEV_CFG(dev)->divider;
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/* FIXME: way to validate prescaler & divider */
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/* Enable the PWM peripheral */
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soc_pmc_peripheral_enable(id);
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/* Configure the clock A that will be used by all 4 channels */
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pwm->PWM_CLK = PWM_CLK_PREA(prescaler) | PWM_CLK_DIVA(divider);
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return 0;
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}
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static const struct pwm_driver_api sam_pwm_driver_api = {
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.pin_set = sam_pwm_pin_set,
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.get_cycles_per_sec = sam_pwm_get_cycles_per_sec,
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};
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#ifdef DT_ATMEL_SAM_PWM_0
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static const struct sam_pwm_config sam_pwm_config_0 = {
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.regs = (Pwm *)DT_ATMEL_SAM_PWM_0_BASE_ADDRESS,
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.id = DT_ATMEL_SAM_PWM_0_PERIPHERAL_ID,
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.prescaler = DT_ATMEL_SAM_PWM_0_PRESCALER,
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.divider = DT_ATMEL_SAM_PWM_0_DIVIDER,
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};
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DEVICE_AND_API_INIT(sam_pwm_0, DT_ATMEL_SAM_PWM_0_LABEL, &sam_pwm_init,
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NULL, &sam_pwm_config_0,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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&sam_pwm_driver_api);
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#endif /* DT_ATMEL_SAM_PWM_0 */
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#ifdef DT_ATMEL_SAM_PWM_1
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static const struct sam_pwm_config sam_pwm_config_1 = {
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.regs = (Pwm *)DT_ATMEL_SAM_PWM_1_BASE_ADDRESS,
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.id = DT_ATMEL_SAM_PWM_1_PERIPHERAL_ID,
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.prescaler = DT_ATMEL_SAM_PWM_1_PRESCALER,
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.divider = DT_ATMEL_SAM_PWM_1_DIVIDER,
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};
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DEVICE_AND_API_INIT(sam_pwm_1, DT_ATMEL_SAM_PWM_1_LABEL, &sam_pwm_init,
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NULL, &sam_pwm_config_1,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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&sam_pwm_driver_api);
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#endif /* DT_ATMEL_SAM_PWM_1 */
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