026105c883
K3 is a common architecture used between different TI processor families Signed-off-by: Grant Ramsay <gramsay@enphaseenergy.com>
40 lines
1,013 B
YAML
40 lines
1,013 B
YAML
# Copyright (c) 2023 Enphase Energy
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# SPDX-License-Identifier: Apache-2.0
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description: |
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TI K3 pinctrl node.
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Pins can be configured using the following macro "K3_PINMUX(offset, value, mux_mode)".
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offset - the pin attribute register offset from the base address.
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value - one of the following:
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PIN_OUTPUT
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PIN_OUTPUT_PULLUP
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PIN_OUTPUT_PULLDOWN
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PIN_INPUT
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PIN_INPUT_PULLUP
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PIN_INPUT_PULLDOWN
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mux_mode - The mux mode for the pin, MUX_MODE_0 -> MUX_MODE_9.
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e.g. for AM62x the pinctrl base address is 0xf4000.
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The default UART0_RX pin is located at 0x000f41c8 (mux mode 0).
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So the configuration would be "K3_PINMUX(0x1c8, PIN_INPUT, MUX_MODE_0)".
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compatible: "ti,k3-pinctrl"
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include: base.yaml
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properties:
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reg:
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required: true
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child-binding:
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description: |
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This binding gives a base representation of the TI K3
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pin configuration.
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properties:
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pinmux:
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required: true
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type: array
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description: |
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TI K3 pin configuration.
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