0369998e61
MIPS (Microprocessor without Interlocked Pipelined Stages) is a instruction set architecture (ISA) developed by MIPS Computer Systems, now MIPS Technologies. This commit provides MIPS architecture support to Zephyr. It is compatible with the MIPS32 Release 1 specification. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
48 lines
1.4 KiB
C
48 lines
1.4 KiB
C
/*
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* Copyright (c) 2021 Antony Pavlov <antonynpavlov@gmail.com>
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*
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* based on arch/riscv/include/offsets_short_arch.h
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_ARCH_MIPS_INCLUDE_OFFSETS_SHORT_ARCH_H_
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#define ZEPHYR_ARCH_MIPS_INCLUDE_OFFSETS_SHORT_ARCH_H_
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#include <offsets.h>
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#define _thread_offset_to_sp \
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(___thread_t_callee_saved_OFFSET + ___callee_saved_t_sp_OFFSET)
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#define _thread_offset_to_s0 \
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(___thread_t_callee_saved_OFFSET + ___callee_saved_t_s0_OFFSET)
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#define _thread_offset_to_s1 \
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(___thread_t_callee_saved_OFFSET + ___callee_saved_t_s1_OFFSET)
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#define _thread_offset_to_s2 \
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(___thread_t_callee_saved_OFFSET + ___callee_saved_t_s2_OFFSET)
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#define _thread_offset_to_s3 \
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(___thread_t_callee_saved_OFFSET + ___callee_saved_t_s3_OFFSET)
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#define _thread_offset_to_s4 \
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(___thread_t_callee_saved_OFFSET + ___callee_saved_t_s4_OFFSET)
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#define _thread_offset_to_s5 \
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(___thread_t_callee_saved_OFFSET + ___callee_saved_t_s5_OFFSET)
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#define _thread_offset_to_s6 \
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(___thread_t_callee_saved_OFFSET + ___callee_saved_t_s6_OFFSET)
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#define _thread_offset_to_s7 \
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(___thread_t_callee_saved_OFFSET + ___callee_saved_t_s7_OFFSET)
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#define _thread_offset_to_s8 \
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(___thread_t_callee_saved_OFFSET + ___callee_saved_t_s8_OFFSET)
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#define _thread_offset_to_swap_return_value \
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(___thread_t_arch_OFFSET + ___thread_arch_t_swap_return_value_OFFSET)
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#endif /* ZEPHYR_ARCH_MIPS_INCLUDE_OFFSETS_SHORT_ARCH_H_ */
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