Tomasz Leman 50f0e223e8 dts: adsp: ace15: remove lp clock ... LP/HP RING OSC clocks were replaced by the ACE IPLL clock. If needed IPLL can be configured to work as low power clock. But right now ACE uses only WOVCRO and IPLL (configured to work as HP RING OSC clock). Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>		2023-09-18 10:35:23 +01:00
..
intel_adsp_ace15_mtpm.dtsi	dts: adsp: ace15: remove lp clock	2023-09-18 10:35:23 +01:00
intel_adsp_ace20_lnl.dtsi	dts: adsp: ace20: replace hp with ipll clock	2023-09-18 10:35:23 +01:00
intel_adsp_cavs.dtsi	dts: xtensa: intel: add HDA DMA interrupt defs for cAVS platforms	2023-08-31 09:59:10 -04:00
intel_adsp_cavs15.dtsi	ace: cavs: dts: Add d-cache and i-cache line size	2022-11-23 15:39:05 -05:00
intel_adsp_cavs18.dtsi	ace: cavs: dts: Add d-cache and i-cache line size	2022-11-23 15:39:05 -05:00
intel_adsp_cavs20.dtsi	ace: cavs: dts: Add d-cache and i-cache line size	2022-11-23 15:39:05 -05:00
intel_adsp_cavs20_jsl.dtsi	ace: cavs: dts: Add d-cache and i-cache line size	2022-11-23 15:39:05 -05:00
intel_adsp_cavs25.dtsi	pm: power-states node needs to be a child of cpus	2023-07-25 09:16:14 +02:00
intel_adsp_cavs25_tgph.dtsi	pm: power-states node needs to be a child of cpus	2023-07-25 09:16:14 +02:00