069bcbcb7f
This adds new NXP mailbox driver for MBOX device. NXP mailbox IP driver supports sending data between cores. It uses 32 bit register to trigger irq to other core. This driver implementation uses 4 bits for channel selection of triggering mode, 4 bits for channel selection of data transfer and rest 24 bits for data. NXP mailbox IP Reference Manual UM11126, Chapter 52. https://www.nxp.com/webapp/Download?colCode=UM11126 Signed-off-by: Tomas Galbicka <tomas.galbicka@nxp.com>
13 lines
562 B
CMake
13 lines
562 B
CMake
# SPDX-License-Identifier: Apache-2.0
|
|
|
|
zephyr_syscall_header(${ZEPHYR_BASE}/include/zephyr/drivers/mbox.h)
|
|
|
|
zephyr_library()
|
|
|
|
zephyr_library_sources_ifdef(CONFIG_USERSPACE mbox_handlers.c)
|
|
zephyr_library_sources_ifdef(CONFIG_MBOX_NRFX_IPC mbox_nrfx_ipc.c)
|
|
zephyr_library_sources_ifdef(CONFIG_MBOX_NXP_S32_MRU mbox_nxp_s32_mru.c)
|
|
zephyr_library_sources_ifdef(CONFIG_MBOX_NXP_IMX_MU mbox_nxp_imx_mu.c)
|
|
zephyr_library_sources_ifdef(CONFIG_MBOX_NXP_MAILBOX mbox_nxp_mailbox.c)
|
|
zephyr_library_sources_ifdef(CONFIG_MBOX_ANDES_PLIC_SW mbox_andes_plic_sw.c)
|