069bcbcb7f
This adds new NXP mailbox driver for MBOX device. NXP mailbox IP driver supports sending data between cores. It uses 32 bit register to trigger irq to other core. This driver implementation uses 4 bits for channel selection of triggering mode, 4 bits for channel selection of data transfer and rest 24 bits for data. NXP mailbox IP Reference Manual UM11126, Chapter 52. https://www.nxp.com/webapp/Download?colCode=UM11126 Signed-off-by: Tomas Galbicka <tomas.galbicka@nxp.com>
32 lines
849 B
Plaintext
32 lines
849 B
Plaintext
# Copyright (c) 2021 Carlo Caione <ccaione@baylibre.com>
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# Copyright 2024 NXP
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# SPDX-License-Identifier: Apache-2.0
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menuconfig MBOX
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bool "Multi-Channel Inter-Processor Mailbox (MBOX) drivers"
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help
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Include multi-channel interrupt-based inter-processor mailboxes
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drivers in system configuration
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if MBOX
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# Include these first so that any properties (e.g. defaults) below can be
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# overridden (by defining symbols in multiple locations)
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source "drivers/mbox/Kconfig.nrfx"
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source "drivers/mbox/Kconfig.nxp_s32"
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source "drivers/mbox/Kconfig.nxp_imx"
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source "drivers/mbox/Kconfig.nxp_mailbox"
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source "drivers/mbox/Kconfig.andes"
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config MBOX_INIT_PRIORITY
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int "MBOX init priority"
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default 40
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help
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MBOX driver device initialization priority.
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module = MBOX
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module-str = mbox
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source "subsys/logging/Kconfig.template.log_config"
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endif # MBOX
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