Ruud Derwig 0076313bcb soc: arc: Increase cpu frequency for nsim_hs_smp ... 0.5 Mhz with 100 ticks per sec leaves 5000 cycles per tick, which broke some tests that assumed more work within 1 tick. Set to 1 Mhz: balance multi-core simulation speed and tick duration. Fixes #27943 Signed-off-by: Ruud Derwig <Ruud.Derwig@synopsys.com>		2020-09-16 14:35:31 -05:00
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arc	soc: arc: Increase cpu frequency for nsim_hs_smp	2020-09-16 14:35:31 -05:00
arm	soc: lpc11u6x: fix pinmux initialization priority	2020-09-14 12:47:32 -05:00
nios2	soc: nios2: Cleanup linker scripts to use new DTS macros	2020-04-30 20:59:13 -05:00
posix	zephyr: replace zephyr integer types with C99 types	2020-06-08 08:23:57 -05:00
riscv	device: Const-ify all device driver instance pointers	2020-09-02 13:48:13 +02:00
x86	boards: x86: Remove gpmrb board	2020-07-30 12:15:01 -04:00
xtensa	soc: intel_apl_adsp: Tweak adsp initialization	2020-09-04 07:55:52 -04:00
Kconfig	timing: introduce timing functions as a generic feature	2020-09-05 13:28:38 -05:00