8185faa0cb
On S32K344, the offset in memory map between each channel is 0x4000 for most channels, but there is specific case is between channel 11 and 12 which is 0x1D4000 instead. As a consequence, 32 channels are divided to two parts: one starts from channel 0 -> 11. The other is from channel 128 to 145. The channel gap is from 12 -> 127. For user and data structures in shim driver, the channel's value comes from 0 --> 31. Above constraint will be counted when interact with the mcux sdk Beside that, the DMAMUX register in this platform is very specific, not in identical with DMAMUX channel, so shim driver is updated to cover this case Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
67 lines
1.6 KiB
YAML
67 lines
1.6 KiB
YAML
# Copyright (c) 2020, NXP
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# SPDX-License-Identifier: Apache-2.0
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description: NXP MCUX EDMA controller
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compatible: "nxp,mcux-edma"
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include: dma-controller.yaml
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properties:
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reg:
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required: true
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description: |
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Specifies base physical address(s) and size of DMA and respective DMAMUX register(s)
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that routes DMA sources
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interrupts:
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required: true
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dma-channels:
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required: true
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dma-requests:
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required: true
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dmamux-reg-offset:
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type: int
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default: 0
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description:
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The offset value for obtaining DMAMUX register index from DMAMUX channel.
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Default value means DMAMUX channel is identical with DMAMUX register index
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channel-gap:
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type: array
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description: |
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On some platforms, there may be a gap in the channels and
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this array specifies the start and end of a single gap
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nxp,mem2mem:
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type: boolean
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description: If the DMA controller supports memory to memory transfer
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nxp,a_on:
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type: boolean
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description: If the DMA controller supports always on
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irq-shared-offset:
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type: int
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default: 0
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description: |
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Describes an offset between two channels share the same interrupt entry.
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Default value means each channel has separate interrupt entry.
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"#dma-cells":
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type: int
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required: true
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description: Number of items to expect in a DMAMUX specifier
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# - #dma-cells : Must be <2>.
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# The 1st cell specifies the DMA channel which will be used
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# The 2nd cell specifies the request source (slot) ID.
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# See the SoC's reference manual for all the supported request sources.
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dma-cells:
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- mux
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- source
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