5d0db517b9
Add a new sifive,plic-1.0.0 binding that inherits from the riscv,plic0 binding. The new binding adds a required riscv,ndev property, which gives the number of external interrupts supported. Use the new binding for microsemi-miv.dtsi (with a value of 31 for riscv,ndev, from http://www.actel.com/ipdocs/MiV_RV32IMAF_L1_AHB_HB.pdf) and riscv32-fe310.dtsi (which already assigns riscv,ndev). Also remove a spurious riscv,ndev assignment from riscv32-litex-vexriscv.dtsi. Also make edtlib and the old scripts/dts/ scripts replace '.' in compatible strings with '_' when generating identifiers. Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
19 lines
391 B
YAML
19 lines
391 B
YAML
# Copyright (c) 2018, SiFive Inc.
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#
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# SPDX-License-Identifier: Apache-2.0
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title: SiFive PLIC
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description: SiFive RISCV-V platform-local interrupt controller
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inherits:
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!include riscv,plic0.yaml
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properties:
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compatible:
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constraint: "sifive,plic-1.0.0"
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riscv,ndev:
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type: int
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description: Number of external interrupts supported
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category: required
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