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zephyr/arch/xtensa/core
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Daniel Leung 5db5e8e109 xtensa: userspace: fix incorrectly passed syscall frame pointer 
Calling z_mrsh_* functions require 7 arguments where the 7th is
the stack frame. Only the first 6 arguments are passed by
registers where the 7th must be done via stack. However, this
is not being done and an incorrect argument was being passed to
the z_mrsh_* functions as stack frame pointer. An obvious issue
would be dumping of stack during kernel oops, as incorrect data
was being printed or crashes due to inaccessible memory. So fix
it by properly populating the stack with correct stack frame
pointer as outgoing argument for the caller of z_mrsh_*
functions.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2024-03-19 22:17:34 -04:00
..
offsets arch: xtensa: Add space for HiFi registers 2024-03-05 10:57:33 +01:00
startup xtensa: rename files with hyphens to underscores 2023-12-13 09:41:24 +01:00
CMakeLists.txt arch: xtensa: save/restore HiFi AudioEngine regs 2024-03-05 10:57:33 +01:00
coredump.c xtensa: rename files with hyphens to underscores 2023-12-13 09:41:24 +01:00
cpu_idle.c arch/xtensa: clean up arch_cpu_idle function 2023-11-20 11:14:41 +01:00
crt1.S xtensa: mmu: Simplify initialization 2023-11-21 15:49:48 +01:00
debug_helpers_asm.S xtensa: rename z_xtensa to simply xtensa 2023-12-13 09:41:24 +01:00
elf.c llext: merge llext_mem and llext_section enums 2023-12-14 19:06:55 +00:00
fatal.c xtensa: remove ARG_UNUSED from arch_syscall_oops 2024-02-01 13:09:53 -06:00
gdbstub.c xtensa: rename z_xtensa_irq to simple xtensa_irq 2023-12-13 09:41:24 +01:00
gen_zsr.py xtensa: only need ZSR_FLUSH if CONFIG_KERNEL_COHERENCE 2024-02-01 13:09:53 -06:00
irq_manage.c xtensa: rename z_xtensa to simply xtensa 2023-12-13 09:41:24 +01:00
irq_offload.c xtensa: irq: Remove CURR_CPU 2024-02-08 09:05:14 +01:00
mem_manage.c xtensa: move to use system cache API support for coherency 2024-02-03 13:42:33 -05:00
mmu.c xtensa: mmu: Fix rasid initial value 2024-03-14 13:24:41 -05:00
ptables.c xtensa: move to use system cache API support for coherency 2024-02-03 13:42:33 -05:00
README_MMU.txt xtensa: rename files with hyphens to underscores 2023-12-13 09:41:24 +01:00
README_WINDOWS.rst xtensa: rename files with hyphens to underscores 2023-12-13 09:41:24 +01:00
smp.c xtensa: move arch_spin_relax into smp.c 2023-12-13 09:41:24 +01:00
syscall_helper.c xtensa: userspace: simplify syscall helper 2023-11-21 15:49:48 +01:00
thread.c xtensa: rename z_xtensa to simply xtensa 2023-12-13 09:41:24 +01:00
timing.c includes: prefer <zephyr/kernel.h> over <zephyr/zephyr.h> 2022-09-05 16:31:47 +02:00
tls.c arch: migrate includes to <zephyr/...> 2022-05-06 19:57:22 +02:00
userspace.S xtensa: userspace: fix incorrectly passed syscall frame pointer 2024-03-19 22:17:34 -04:00
vector_handlers.c xtensa: add support for cores without NMI 2024-02-28 17:35:54 +00:00
window_vectors.S arch/xtensa: Rename "ALLOCA" ZSR to "A0SAVE" 2023-11-21 15:49:48 +01:00
xcc_stubs.c arch: migrate includes to <zephyr/...> 2022-05-06 19:57:22 +02:00
xtensa_asm2_util.S arch: xtensa: save/restore HiFi AudioEngine regs 2024-03-05 10:57:33 +01:00
xtensa_backtrace.c xtensa: rename z_xtensa to simply xtensa 2023-12-13 09:41:24 +01:00
xtensa_hifi.S arch: xtensa: save/restore HiFi AudioEngine regs 2024-03-05 10:57:33 +01:00
xtensa_intgen.py include: add zephyr/ on script generated #include 2022-05-27 15:20:27 -07:00
xtensa_intgen.tmpl xtensa: Interrupt generator script and output for qemu & esp32 2018-02-16 10:44:29 -05:00