Kai Vehmanen be881d4cf2 arch: xtensa: add isync to interrupt vector ... On Intel ADSP platforms, additional "isync" is needed in interrupt vector to synchronize icache when core is woken up from deeper sleep state by an interrupt. This is only needed if DSP clock gating is enabled. Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>		2024-03-15 21:45:57 -04:00
..
kernel_arch_func.h	xtensa: rename z_xtensa to simply xtensa	2023-12-13 09:41:24 +01:00
offsets_short_arch.h	xtensa: Enable userspace	2023-11-21 15:49:48 +01:00
xtensa_asm2_context.h	arch: xtensa: Add space for HiFi registers	2024-03-05 10:57:33 +01:00
xtensa_asm2_s.h	arch: xtensa: add isync to interrupt vector	2024-03-15 21:45:57 -04:00
xtensa_backtrace.h	xtensa: rename z_xtensa to simply xtensa	2023-12-13 09:41:24 +01:00
xtensa_internal.h	xtensa: rename z_xtensa to simply xtensa	2023-12-13 09:41:24 +01:00
xtensa_mmu_priv.h	xtensa: mmu: Optimize autorefill invalidation	2024-01-19 13:50:02 +01:00