dd0923d7ad
Add devicetree node for the accompanying, ssd1306-based display board connected to connector P4. Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
642 lines
13 KiB
Plaintext
642 lines
13 KiB
Plaintext
/*
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* Copyright 2023 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <arm/nxp/nxp_s32k344_m7.dtsi>
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#include <dt-bindings/gpio/gpio.h>
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#include <zephyr/dt-bindings/input/input-event-codes.h>
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#include <freq.h>
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#include <dt-bindings/pwm/pwm.h>
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#include "mr_canhubk3-pinctrl.dtsi"
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#include <zephyr/dt-bindings/sensor/qdec_nxp_s32.h>
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/ {
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model = "NXP MR-CANHUBK3";
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compatible = "nxp,mr_canhubk3";
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chosen {
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zephyr,sram = &sram0_1;
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zephyr,flash = &flash0;
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zephyr,itcm = &itcm;
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zephyr,dtcm = &dtcm;
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zephyr,code-partition = &code_partition;
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zephyr,console = &lpuart2;
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zephyr,shell-uart = &lpuart2;
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zephyr,flash-controller = &mx25l6433f;
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zephyr,canbus = &flexcan0;
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zephyr,display = &ssd1306;
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};
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aliases {
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dma0 = &edma0;
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led0 = &user_led1_red;
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led1 = &user_led1_green;
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led2 = &user_led1_blue;
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sw0 = &user_button_1;
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sw1 = &user_button_2;
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watchdog0 = &fs26_wdt;
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/* For pwm test suites */
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pwm-0 = &emios0_pwm;
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red-pwm-led = &user_led1_red_pwm;
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green-pwm-led = &user_led1_green_pwm;
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blue-pwm-led = &user_led1_blue_pwm;
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pwm-led0 = &user_led1_blue_pwm;
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qdec0 = &qdec0;
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};
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leds {
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compatible = "gpio-leds";
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user_led1_green: user_led1_green {
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gpios = <&gpioa_h 11 GPIO_ACTIVE_LOW>;
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label = "User RGB LED1 GREEN";
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};
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user_led1_blue: user_led1_blue {
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gpios = <&gpioe_l 12 GPIO_ACTIVE_LOW>;
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label = "User RGB LED1 BLUE";
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};
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user_led1_red: user_led1_red {
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gpios = <&gpioe_l 14 GPIO_ACTIVE_LOW>;
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label = "User RGB LED1 RED";
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};
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can_led0: can_led0 {
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gpios = <&gpioc_h 2 GPIO_ACTIVE_LOW>;
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label = "CAN LED0";
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};
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can_led1: can_led1 {
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gpios = <&gpioe_l 5 GPIO_ACTIVE_LOW>;
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label = "CAN LED1";
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};
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can_led2: can_led2 {
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gpios = <&gpiod_h 4 GPIO_ACTIVE_LOW>;
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label = "CAN LED2";
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};
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can_led3: can_led3 {
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gpios = <&gpiob_h 8 GPIO_ACTIVE_LOW>;
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label = "CAN LED3";
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};
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can_led4: can_led4 {
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gpios = <&gpiob_h 10 GPIO_ACTIVE_LOW>;
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label = "CAN LED4";
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};
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can_led5: can_led5 {
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gpios = <&gpiod_h 15 GPIO_ACTIVE_LOW>;
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label = "CAN LED5";
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};
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};
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/* gpio-leds and pwm-leds are the same RGB LED and cannot be used at the same time. */
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pwmleds {
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compatible = "pwm-leds";
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user_led1_blue_pwm: user_led1_blue {
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pwms = <&emios1_pwm 5 PWM_MSEC(20) PWM_POLARITY_INVERTED>;
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};
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user_led1_green_pwm: user_led1_green {
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pwms = <&emios1_pwm 10 PWM_MSEC(20) PWM_POLARITY_INVERTED>;
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};
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user_led1_red_pwm: user_led1_red {
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pwms = <&emios0_pwm 19 PWM_MSEC(20) PWM_POLARITY_INVERTED>;
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};
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};
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qdec0: qdec0 {
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compatible = "nxp,qdec-s32";
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pinctrl-0 = <&qdec_s32>;
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pinctrl-names = "default";
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micro-ticks-per-rev = <685440000>;
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status = "okay";
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trgmux = <&trgmux>;
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trgmux-io-config =
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<0 TRGMUX_IP_OUTPUT_EMIOS0_CH5_9_IPP_IND_CH6 TRGMUX_IP_INPUT_LCU1_LC0_OUT_I2>,
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<1 TRGMUX_IP_OUTPUT_EMIOS0_CH5_9_IPP_IND_CH7 TRGMUX_IP_INPUT_LCU1_LC0_OUT_I3>,
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<2 TRGMUX_IP_OUTPUT_LCU1_0_INP_I0 TRGMUX_IP_INPUT_SIUL2_IN2>,
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<3 TRGMUX_IP_OUTPUT_LCU1_0_INP_I1 TRGMUX_IP_INPUT_SIUL2_IN3>;
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lcu = <&lcu1>;
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lcu-input-idx =
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<LCU_IP_IN_0 LCU_IP_IN_1
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LCU_IP_IN_2 LCU_IP_IN_3>;
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lcu-mux-sel =
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<LCU_IP_MUX_SEL_LU_IN_0 LCU_IP_MUX_SEL_LU_IN_1
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LCU_IP_MUX_SEL_LU_OUT_0 LCU_IP_MUX_SEL_LU_OUT_1>;
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lcu-output-filter-config =
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/* LCU Out HW ID, Rise Filter, Fall Filter */
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<0 5 5>, /* LCU O0 */
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<1 5 5>, /* LCU O1 */
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<2 2 2>, /* LCU O2 */
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<3 2 2>; /* LCU O3 */
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emios = <&emios0>;
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/*
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* eMios channel numbers for qdec should be beyond the channel numbers
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* used by the emios pwm
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*/
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emios-channels = <6 7>;
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};
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gpio_keys {
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compatible = "gpio-keys";
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user_button_1: button_0 {
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label = "User SW1";
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gpios = <&gpiod_l 15 GPIO_ACTIVE_HIGH>;
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zephyr,code = <INPUT_KEY_0>;
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};
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user_button_2: button_1 {
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label = "User SW2";
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gpios = <&gpioa_h 9 GPIO_ACTIVE_HIGH>;
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zephyr,code = <INPUT_KEY_1>;
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};
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};
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can_phy0: can-phy0 {
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compatible = "nxp,tja1443", "can-transceiver-gpio";
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enable-gpios = <&gpioc_h 8 GPIO_ACTIVE_HIGH>;
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standby-gpios = <&gpioc_h 5 GPIO_ACTIVE_LOW>;
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max-bitrate = <5000000>;
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#phy-cells = <0>;
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};
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can_phy1: can-phy1 {
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compatible = "nxp,tja1443", "can-transceiver-gpio";
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enable-gpios = <&gpiod_l 2 GPIO_ACTIVE_HIGH>;
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standby-gpios = <&gpiod_h 7 GPIO_ACTIVE_LOW>;
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max-bitrate = <5000000>;
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#phy-cells = <0>;
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};
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can_phy2: can-phy2 {
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compatible = "nxp,tja1463", "can-transceiver-gpio";
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enable-gpios = <&gpiod_l 4 GPIO_ACTIVE_HIGH>;
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standby-gpios = <&gpiod_h 6 GPIO_ACTIVE_LOW>;
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max-bitrate = <8000000>;
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#phy-cells = <0>;
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};
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can_phy3: can-phy3 {
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compatible = "nxp,tja1463", "can-transceiver-gpio";
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enable-gpios = <&gpiob_l 0 GPIO_ACTIVE_HIGH>;
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standby-gpios = <&gpiob_l 1 GPIO_ACTIVE_LOW>;
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max-bitrate = <8000000>;
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#phy-cells = <0>;
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};
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can_phy4: can-phy4 {
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compatible = "nxp,tja1153", "can-transceiver-gpio";
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enable-gpios = <&gpioc_h 10 GPIO_ACTIVE_HIGH>;
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standby-gpios = <&gpioc_h 9 GPIO_ACTIVE_LOW>;
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max-bitrate = <2000000>;
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#phy-cells = <0>;
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};
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can_phy5: can-phy5 {
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compatible = "nxp,tja1153", "can-transceiver-gpio";
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enable-gpios = <&gpioe_h 1 GPIO_ACTIVE_HIGH>;
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standby-gpios = <&gpiod_h 14 GPIO_ACTIVE_LOW>;
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max-bitrate = <2000000>;
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#phy-cells = <0>;
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};
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};
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&flash0 {
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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ivt_header: partition@0 {
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label = "ivt-header";
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reg = <0x00000000 0x100>;
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};
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code_partition: partition@100 {
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label = "code-partition";
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reg = <0x00000100 (DT_SIZE_K(4048) - 0x100)>;
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};
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};
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};
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&gpioa_h {
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status = "okay";
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};
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&gpioe_l {
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status = "okay";
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};
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/* Enable gpio to control the CAN transceivers and LEDs */
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&gpiob_h {
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status = "okay";
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};
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&gpioc_h {
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status = "okay";
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};
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&gpiod_l {
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status = "okay";
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};
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&gpiod_h {
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status = "okay";
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};
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&gpiob_l {
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status = "okay";
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};
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&gpioe_h {
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status = "okay";
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};
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&eirq0 {
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pinctrl-0 = <&eirq0_default>;
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pinctrl-names = "default";
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status = "okay";
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};
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&lpuart0 {
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pinctrl-0 = <&lpuart0_default>;
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pinctrl-names = "default";
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dmas = <&edma0 0 37>, <&edma0 1 38>;
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dma-names = "tx", "rx";
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};
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&lpuart1 {
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pinctrl-0 = <&lpuart1_default>;
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pinctrl-names = "default";
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dmas = <&edma0 2 39>, <&edma0 3 40>;
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dma-names = "tx", "rx";
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};
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&lpuart2 {
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pinctrl-0 = <&lpuart2_default>;
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pinctrl-names = "default";
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current-speed = <115200>;
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dmas = <&edma0 16 38>, <&edma0 17 39>;
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dma-names = "tx", "rx";
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status = "okay";
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};
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&lpuart9 {
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pinctrl-0 = <&lpuart9_default>;
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pinctrl-names = "default";
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/*
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* LPUART 1 and 9 share the same DMA source for TX
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* and RX, using UART async API for both instances
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* should be careful.
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*/
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dmas = <&edma0 4 39>, <&edma0 5 40>;
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dma-names = "tx", "rx";
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};
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&lpuart10 {
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pinctrl-0 = <&lpuart10_default>;
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pinctrl-names = "default";
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/*
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* LPUART 2 and 10 share the same DMA source for TX
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* and RX, using UART async API for both instances
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* should be careful.
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*/
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dmas = <&edma0 18 38>, <&edma0 19 39>;
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dma-names = "tx", "rx";
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};
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&lpuart13 {
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pinctrl-0 = <&lpuart13_default>;
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pinctrl-names = "default";
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dmas = <&edma0 20 44>, <&edma0 21 45>;
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dma-names = "tx", "rx";
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};
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&lpuart14 {
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pinctrl-0 = <&lpuart14_default>;
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pinctrl-names = "default";
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dmas = <&edma0 22 46>, <&edma0 23 47>;
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dma-names = "tx", "rx";
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};
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&qspi0 {
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pinctrl-0 = <&qspi0_default>;
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pinctrl-names = "default";
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data-rate = "SDR";
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a-rx-clock-source = "LOOPBACK";
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a-dll-mode = "BYPASSED";
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ahb-buffers-masters = <0 1 2 3>;
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ahb-buffers-sizes = <0 0 0 256>;
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ahb-buffers-all-masters;
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status = "okay";
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mx25l6433f: mx25l6433f@0 {
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compatible = "nxp,s32-qspi-nor";
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reg = <0>;
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size = <DT_SIZE_M(64)>;
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jedec-id = [c2 20 17];
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quad-enable-requirements = "S1B6";
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readoc = "1-4-4";
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writeoc = "1-4-4";
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has-32k-erase;
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status = "okay";
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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storage_partition: partition@0 {
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label = "storage";
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reg = <0x0 0x100000>;
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};
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};
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};
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};
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&flexcan0 {
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pinctrl-0 = <&flexcan0_default>;
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pinctrl-names = "default";
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phys = <&can_phy0>;
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bus-speed = <125000>;
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bus-speed-data = <1000000>;
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status = "okay";
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};
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&flexcan1 {
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pinctrl-0 = <&flexcan1_default>;
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pinctrl-names = "default";
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phys = <&can_phy1>;
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bus-speed = <125000>;
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bus-speed-data = <1000000>;
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};
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&flexcan2 {
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pinctrl-0 = <&flexcan2_default>;
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pinctrl-names = "default";
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phys = <&can_phy2>;
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bus-speed = <125000>;
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bus-speed-data = <1000000>;
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};
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&flexcan3 {
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pinctrl-0 = <&flexcan3_default>;
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pinctrl-names = "default";
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phys = <&can_phy3>;
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bus-speed = <125000>;
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bus-speed-data = <1000000>;
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};
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&flexcan4 {
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pinctrl-0 = <&flexcan4_default>;
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pinctrl-names = "default";
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phys = <&can_phy4>;
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bus-speed = <125000>;
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bus-speed-data = <1000000>;
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};
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&flexcan5 {
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pinctrl-0 = <&flexcan5_default>;
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pinctrl-names = "default";
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phys = <&can_phy5>;
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bus-speed = <125000>;
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bus-speed-data = <1000000>;
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};
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&lpi2c0 {
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pinctrl-0 = <&lpi2c0_default>;
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pinctrl-names = "default";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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status = "okay";
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ssd1306: ssd1306@3c {
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compatible = "solomon,ssd1306fb";
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reg = <0x3c>;
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width = <128>;
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height = <32>;
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segment-offset = <0>;
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page-offset = <0>;
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display-offset = <0>;
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multiplex-ratio = <31>;
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segment-remap;
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com-invdir;
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com-sequential;
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prechargep = <0x22>;
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};
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};
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&lpi2c1 {
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pinctrl-0 = <&lpi2c1_default>;
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pinctrl-names = "default";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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};
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&lpspi1 {
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pinctrl-0 = <&lpspi1_default>;
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pinctrl-names = "default";
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data-pin-config = "sdo-in,sdi-out";
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};
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&lpspi2 {
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pinctrl-0 = <&lpspi2_default>;
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pinctrl-names = "default";
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data-pin-config = "sdo-in,sdi-out";
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};
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&lpspi3 {
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pinctrl-0 = <&lpspi3_default>;
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pinctrl-names = "default";
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data-pin-config = "sdo-in,sdi-out";
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status = "okay";
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fs26_wdt: watchdog@0 {
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compatible = "nxp,fs26-wdog";
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reg = <0>;
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spi-max-frequency = <DT_FREQ_M(5)>;
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type = "challenger";
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int-gpios = <&gpioa_h 2 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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};
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&lpspi4 {
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pinctrl-0 = <&lpspi4_default>;
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pinctrl-names = "default";
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data-pin-config = "sdo-in,sdi-out";
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};
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&lpspi5 {
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pinctrl-0 = <&lpspi5_default>;
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pinctrl-names = "default";
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data-pin-config = "sdo-in,sdi-out";
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};
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&emac0 {
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pinctrl-0 = <&emac0_default>;
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pinctrl-names = "default";
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phy-connection-type = "rmii";
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local-mac-address = [02 04 9f aa bb cc];
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phy-handle = <&phy>;
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status = "okay";
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};
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&mdio0 {
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pinctrl-0 = <&mdio0_default>;
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pinctrl-names = "default";
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status = "okay";
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phy: ethernet-phy@12 {
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compatible = "nxp,tja1103";
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status = "okay";
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reg = <0x12>;
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int-gpios = <&gpiod_l 5 GPIO_ACTIVE_LOW>;
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master-slave = "slave";
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};
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};
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&emios0 {
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clock-divider = <200>;
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status = "okay";
|
|
|
|
master_bus {
|
|
/*
|
|
* Timebase for PWM led, setting clock 50KHz for internal counter,
|
|
* default period is 1000 cycles <-> 20ms.
|
|
*/
|
|
emios0_bus_a {
|
|
mode = "MCB_UP_COUNTER";
|
|
prescaler = <16>;
|
|
period = <1000>;
|
|
status = "okay";
|
|
};
|
|
};
|
|
|
|
emios0_pwm: pwm {
|
|
pinctrl-0 = <&emios0_default>;
|
|
pinctrl-names = "default";
|
|
status = "okay";
|
|
|
|
/* Default clock for internal counter for PWM channel 0-7 is 100Khz */
|
|
pwm_0 {
|
|
channel = <0>;
|
|
pwm-mode = "OPWFMB";
|
|
period = <65535>;
|
|
duty-cycle = <0>;
|
|
prescaler = <8>;
|
|
polarity = "ACTIVE_HIGH";
|
|
};
|
|
|
|
pwm_1 {
|
|
channel = <1>;
|
|
pwm-mode = "OPWFMB";
|
|
period = <65535>;
|
|
duty-cycle = <0>;
|
|
prescaler = <8>;
|
|
polarity = "ACTIVE_HIGH";
|
|
};
|
|
|
|
pwm_2 {
|
|
channel = <2>;
|
|
pwm-mode = "OPWFMB";
|
|
period = <65535>;
|
|
duty-cycle = <0>;
|
|
prescaler = <8>;
|
|
polarity = "ACTIVE_HIGH";
|
|
};
|
|
|
|
pwm_3 {
|
|
channel = <3>;
|
|
pwm-mode = "OPWFMB";
|
|
period = <65535>;
|
|
duty-cycle = <0>;
|
|
prescaler = <8>;
|
|
polarity = "ACTIVE_HIGH";
|
|
};
|
|
|
|
pwm_4 {
|
|
channel = <4>;
|
|
pwm-mode = "OPWFMB";
|
|
period = <65535>;
|
|
duty-cycle = <0>;
|
|
prescaler = <8>;
|
|
polarity = "ACTIVE_HIGH";
|
|
};
|
|
|
|
pwm_5 {
|
|
channel = <5>;
|
|
pwm-mode = "OPWFMB";
|
|
period = <65535>;
|
|
duty-cycle = <0>;
|
|
prescaler = <8>;
|
|
polarity = "ACTIVE_HIGH";
|
|
};
|
|
|
|
rgb_red {
|
|
channel = <19>;
|
|
master-bus = <&emios0_bus_a>;
|
|
duty-cycle = <0>;
|
|
pwm-mode = "OPWMB";
|
|
polarity = "ACTIVE_LOW";
|
|
};
|
|
};
|
|
};
|
|
|
|
&emios1 {
|
|
clock-divider = <200>;
|
|
status = "okay";
|
|
|
|
master_bus {
|
|
/*
|
|
* Timebase for PWM led, setting clock 50KHz for internal counter,
|
|
* default period is 1000 cycles <-> 20ms.
|
|
*/
|
|
emios1_bus_a {
|
|
prescaler = <16>;
|
|
mode = "MCB_UP_COUNTER";
|
|
period = <1000>;
|
|
status = "okay";
|
|
};
|
|
|
|
emios1_bus_f {
|
|
prescaler = <16>;
|
|
mode = "MCB_UP_COUNTER";
|
|
period = <1000>;
|
|
status = "okay";
|
|
};
|
|
};
|
|
|
|
emios1_pwm: pwm {
|
|
pinctrl-0 = <&emios1_default>;
|
|
pinctrl-names = "default";
|
|
status = "okay";
|
|
|
|
rgb_green {
|
|
channel = <10>;
|
|
master-bus = <&emios1_bus_a>;
|
|
duty-cycle = <0>;
|
|
pwm-mode = "OPWMB";
|
|
polarity = "ACTIVE_LOW";
|
|
};
|
|
|
|
rgb_blue {
|
|
channel = <5>;
|
|
master-bus = <&emios1_bus_f>;
|
|
duty-cycle = <0>;
|
|
pwm-mode = "OPWMB";
|
|
polarity = "ACTIVE_LOW";
|
|
};
|
|
};
|
|
};
|
|
|
|
&lcu1 {
|
|
status = "okay";
|
|
};
|
|
|
|
&trgmux {
|
|
status = "okay";
|
|
};
|
|
|
|
&edma0 {
|
|
status = "okay";
|
|
};
|