Francois Ramu 1798ecbd77 boards: arm: nucleo_f746zg change the sysclock for can timings ... Because of CAN bus clock, some bitrate values might not not give a valid timing calculation depending on the CAN bus freq. The sysclock is changed to the highest common value between USB 48MHz and CAN. The result is a sysclock of 192MHz. Then is USB at 48MHz and the CAN bus freq is the APB1 (PCLK1) at 48MHz Signed-off-by: Francois Ramu <francois.ramu@st.com>		2023-02-11 07:57:16 +09:00
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doc	boards: convert images to JPEG and reduce image size	2022-08-29 10:18:18 +02:00
support	boards: arm: nucleo_f746zg: Created new board	2018-10-25 07:33:30 +01:00
arduino_r3_connector.dtsi	devicetree: tree-wide: add nexus map properties for arduino headers	2019-10-22 14:40:41 -05:00
board.cmake	boards: arm: st, stm32: add jlink runner args	2019-04-19 13:56:28 -05:00
Kconfig.board	kconfig: Clean up header comments and make them consistent	2019-11-04 17:31:27 -05:00
Kconfig.defconfig	drivers/ethernet: stm32: Enable Kconfig symbol ETH_STM32_HAL using dts	2020-07-24 12:03:33 +02:00
nucleo_f746zg.dts	boards: arm: nucleo_f746zg change the sysclock for can timings	2023-02-11 07:57:16 +09:00
nucleo_f746zg.yaml	boards: stm32 adding dac features on nucleo boards nucleo_f746zg	2022-03-10 13:30:06 -05:00
nucleo_f746zg_defconfig	boards: stm32: Remove use of CONFIG_PINMUX	2021-11-26 11:36:42 +01:00