906ee53834
Use a new property, "clock-mux" to select the clock mux for the SAI.
Previously, the clock mux was being selected using the "bits" specifier
of the "clocks" phandle property, which is not the purpose of this
specifier. This can be shown by the regression introduced by 5bebbb91,
which changed the "bits" field to the clock gate shift (which is the
intended meaning).
This incidently worked for the SAI1 and SAI3 peripherals, as the lower 2
bits of the correct clock source selection (0b10) are the same as the new
value placed in the "bit" specifier. For SAI2, the clock source was
switched to PLL3 PDF0 by this change.
To resolve this, use an explict "clock-mux" property for this selection.
Fixes #63541
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
68 lines
1.2 KiB
YAML
68 lines
1.2 KiB
YAML
# Copyright 2021,2023 NXP
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# SPDX-License-Identifier: Apache-2.0
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description: NXP mcux SAI-I2S controller
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compatible: "nxp,mcux-i2s"
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include: [i2s-controller.yaml, pinctrl-device.yaml]
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properties:
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reg:
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required: true
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interrupts:
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required: true
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dma-names:
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required: true
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nxp,tx-dma-channel:
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type: int
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required: true
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description: tx dma channel number
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nxp,rx-dma-channel:
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type: int
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required: true
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description: rx dma channel number
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nxp,tx-sync-mode:
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type: boolean
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description: tx sync mode
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nxp,rx-sync-mode:
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type: boolean
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description: rx sync mode
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pre-div:
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type: int
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description: pre divider
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podf:
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type: int
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description: post-divider fraction
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pll-clocks:
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type: phandle-array
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description: pll settings
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specifier-space: pll-clock
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pll-clock-names:
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type: string-array
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description: Provided names of pll-clock specifiers
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pinmuxes:
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type: phandle-array
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specifier-space: pinmux
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description: iomux settings
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nxp,tx-channel:
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type: int
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description: tx channel the maximum number is SOC dependent
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clock-mux:
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required: true
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type: int
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description: Clock mux source for SAI root clock
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