zephyr/dts/riscv
Jimmy Zheng ca72a0a47f dts: riscv: andes_v5: update andes_v5_ae350.dtsi
Fix mtimer lack of interrupts-extended and make syscon compatilbe to
atcsmu100.

Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
2023-07-17 10:10:31 +00:00
..
andes dts: riscv: andes_v5: update andes_v5_ae350.dtsi 2023-07-17 10:10:31 +00:00
efinix dts: riscv: add a initial SoC dtsi for Efinix Sapphire SoC 2023-06-27 12:09:57 +00:00
espressif dts: Add missing adc dt-bindings include 2023-04-20 10:48:33 +02:00
gigadevice dts: Add missing adc dt-bindings include 2023-04-20 10:48:33 +02:00
ite drivers/crypto/it8xxx2: add support for SHA256 hardware accelerator 2023-07-07 09:24:47 +02:00
lowrisc dts: riscv: lowrisc: Add pwrmgr node to OpenTitan Earlgrey devicetree 2023-05-26 09:45:25 -04:00
microchip dts: riscv: introduce PolarFire SoC I2C interface 2023-06-23 12:31:36 -04:00
niosv dts: riscv: Add dts support for INTEL Nios V/g 2023-06-17 07:34:05 -04:00
openisa dts: riscv: Remove label property from devicetrees 2022-07-26 12:57:23 -05:00
sifive dts: riscv: sifive: fu740: add more cpus 2023-04-12 13:06:29 +02:00
starfive dts: riscv: starfive: align clint description with Linux 2022-08-02 09:12:31 +02:00
telink dts: riscv: telink: add DT entry for machine timer 2022-08-02 09:12:31 +02:00
neorv32.dtsi dts: riscv: neorv32: define machine timer 2022-08-02 09:12:31 +02:00
riscv32-litex-vexriscv.dtsi dts: riscv: Remove label property from devicetrees 2022-07-26 12:57:23 -05:00
virt.dtsi dts: riscv: virt: use sifive,clint0 2022-08-02 09:12:31 +02:00