Daniel Leung d59e7be1ec soc: xtensa/dc233c: turn on i-cache and d-cache ... The DC233C core has support for both i-cache and d-cache. So mark it as such so we can test caching of Xtensa in QEMU. Signed-off-by: Daniel Leung <daniel.leung@intel.com>		2023-12-18 12:25:04 +01:00
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dc233c	soc: xtensa/dc233c: turn on i-cache and d-cache	2023-12-18 12:25:04 +01:00
espressif_esp32	xtensa: rename files with hyphens to underscores	2023-12-13 09:41:24 +01:00
intel_adsp	intel_adsp: lnl: add missing definition for lnl	2023-12-14 22:22:22 +09:00
nxp_adsp	xtensa: rename z_xtensa_irq to simple xtensa_irq	2023-12-13 09:41:24 +01:00
sample_controller	cmake: cleanup and simplify the standard include logic in Zephyr	2023-11-06 18:57:30 -05:00
CMakeLists.txt	soc/xtensa/intel_adsp: Upstream updates	2020-10-21 06:38:53 -04:00