67268f5cbd
This adds a check and option for edge triggered interrupts Signed-off-by: Joshua Lilly <jgl@meta.com>
19 lines
440 B
YAML
19 lines
440 B
YAML
# Copyright (c) 2018, SiFive Inc.
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# SPDX-License-Identifier: Apache-2.0
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description: SiFive RISCV-V platform-local interrupt controller
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compatible: "sifive,plic-1.0.0"
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include: riscv,plic0.yaml
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properties:
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riscv,ndev:
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type: int
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description: Number of external interrupts supported
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required: true
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riscv,trigger-reg-offset:
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type: int
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default: 4224
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description: Offset of the trigger type register if supported
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