zephyr/soc/riscv/common
Greter Raffael 899ee686d8 riscv: irq: Adjust initialization of mtvec in non-legacy CLIC
If CONFIG_LEGACY_CLIC is disabled, i.e. we adhere to the current CLIC
spec, the mode bits of mtvec have to be 0x3. Everything else is
reserved. Therefore if CONFIG_RISCV_VECTORED_MODE is enabled, the
current implementation is correct. If CONFIG_RISCV_VECTORED_MODE is
disabled, the mode bits have to be set, too.

Signed-off-by: Greter Raffael <rgreter@baumer.com>
2024-01-18 10:53:27 +01:00
..
riscv-privileged riscv: irq: Adjust initialization of mtvec in non-legacy CLIC 2024-01-18 10:53:27 +01:00
CMakeLists.txt arch: riscv: introduce RISCV_PRIVILEGED 2024-01-09 09:40:07 +01:00
Kconfig soc: riscv: move privileged code to common folder 2024-01-09 09:40:07 +01:00