d0fe965b9f
Microchip MEC172x has a modified eSPI SAF hardware implementation. Hardware changes include multiple clock dividers for each SPI flash device and data transfer using QMSPI local DMA. espi reset interrupt is made a higer priority in MEC172x devicetree because espi reset event resets all espi hardware and we don't to want to service any other espi interrupt blocks when espi reset occurs. Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com> |
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| arc/synopsys | ||
| arm | ||
| arm64 | ||
| bindings | ||
| common | ||
| nios2/intel | ||
| posix | ||
| riscv | ||
| sparc/gaisler | ||
| x86/intel | ||
| xtensa | ||
| binding-template.yaml | ||
| Kconfig | ||