2455436337
This commit refactors the Intel SSP DAI driver to support dynamic management of SSP IP. This change additionally separates the management of the DAI part from the management part of the SSP IP. Key changes: - Add new static functions to manage SSP IP power. - Update the DAI SSP configuration functions to use the new management approach. - Update device tree bindings and instances to reflect the new SSP IP management mechanism. Signed-off-by: Damian Nikodem <damian.nikodem@intel.com>
670 lines
14 KiB
Plaintext
670 lines
14 KiB
Plaintext
/*
|
|
* Copyright (c) 2022 Intel Corporation
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
#include <xtensa/xtensa.dtsi>
|
|
#include <mem.h>
|
|
|
|
/ {
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
cpu0: cpu@0 {
|
|
device_type = "cpu";
|
|
compatible = "cdns,tensilica-xtensa-lx7";
|
|
reg = <0>;
|
|
cpu-power-states = <&d0i3 &d3>;
|
|
i-cache-line-size = <64>;
|
|
d-cache-line-size = <64>;
|
|
};
|
|
|
|
cpu1: cpu@1 {
|
|
device_type = "cpu";
|
|
compatible = "cdns,tensilica-xtensa-lx7";
|
|
reg = <1>;
|
|
cpu-power-states = <&d0i3 &d3>;
|
|
};
|
|
|
|
cpu2: cpu@2 {
|
|
device_type = "cpu";
|
|
compatible = "cdns,tensilica-xtensa-lx7";
|
|
reg = <2>;
|
|
cpu-power-states = <&d0i3 &d3>;
|
|
};
|
|
|
|
power-states {
|
|
d0i3: idle {
|
|
compatible = "zephyr,power-state";
|
|
power-state-name = "runtime-idle";
|
|
min-residency-us = <200>;
|
|
exit-latency-us = <100>;
|
|
};
|
|
/* PM_STATE_SOFT_OFF can be entered only by calling pm_state_force.
|
|
* The procedure is triggered by IPC from the HOST (SET_DX).
|
|
*/
|
|
d3: off {
|
|
compatible = "zephyr,power-state";
|
|
power-state-name = "soft-off";
|
|
min-residency-us = <0>;
|
|
exit-latency-us = <0>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|
|
|
|
sram0: memory@a0020000 {
|
|
device_type = "memory";
|
|
compatible = "mmio-sram";
|
|
reg = <0xa0020000 DT_SIZE_K(2816)>;
|
|
};
|
|
|
|
sram0virtual: virtualmemory@a0020000 {
|
|
device_type = "memory";
|
|
compatible = "mmio-sram";
|
|
reg = <0xa0020000 DT_SIZE_K(8192)>;
|
|
};
|
|
|
|
sram1: memory@a0000000 {
|
|
device_type = "memory";
|
|
compatible = "mmio-sram";
|
|
reg = <0xa0000000 DT_SIZE_K(64)>;
|
|
};
|
|
|
|
sysclk: system-clock {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <38400000>;
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
clkctl: clkctl {
|
|
compatible = "intel,adsp-shim-clkctl";
|
|
adsp-clkctl-clk-wovcro = <0>;
|
|
adsp-clkctl-clk-ipll = <1>;
|
|
adsp-clkctl-freq-enc = <0xc 0x4>;
|
|
adsp-clkctl-freq-mask = <0x0 0x0>;
|
|
adsp-clkctl-freq-default = <1>;
|
|
adsp-clkctl-freq-lowest = <0>;
|
|
wovcro-supported;
|
|
};
|
|
|
|
audioclk: audio-clock {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <24576000>;
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
pllclk: pll-clock {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <96000000>;
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
IMR1: memory@A1000000 {
|
|
compatible = "intel,adsp-imr";
|
|
reg = <0xA1000000 DT_SIZE_M(16)>;
|
|
block-size = <0x1000>;
|
|
zephyr,memory-region = "IMR1";
|
|
};
|
|
|
|
soc {
|
|
core_intc: core_intc@0 {
|
|
compatible = "cdns,xtensa-core-intc";
|
|
reg = <0x00 0x400>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
};
|
|
|
|
dmic0: dmic0@10000 {
|
|
compatible = "intel,dai-dmic";
|
|
reg = <0x10000 0x8000>;
|
|
shim = <0xC000>;
|
|
fifo = <0x0008>;
|
|
interrupts = <0x08 0 0>;
|
|
interrupt-parent = <&ace_intc>;
|
|
power-domain = <&hub_ulp_domain>;
|
|
};
|
|
|
|
dmic1: dmic1@10000 {
|
|
compatible = "intel,dai-dmic";
|
|
reg = <0x10000 0x8000>;
|
|
shim = <0xC000>;
|
|
fifo = <0x0108>;
|
|
interrupts = <0x09 0 0>;
|
|
interrupt-parent = <&ace_intc>;
|
|
power-domain = <&hub_ulp_domain>;
|
|
};
|
|
|
|
/*
|
|
* FIXME this is modeling individual alh channels/instances
|
|
* with node labels, which has problems. A better representation
|
|
* is discussed here:
|
|
*
|
|
* https://github.com/zephyrproject-rtos/zephyr/pull/50287#discussion_r974591009
|
|
*
|
|
* The hardware actually supports 16 ALH streams/FIFOs. Below description does
|
|
* not fully represent hardware capabilities and is expected to be modified.
|
|
*/
|
|
alh0: alh0@24400 {
|
|
compatible = "intel,alh-dai";
|
|
reg = <0x00024400 0x00024600>;
|
|
status = "okay";
|
|
};
|
|
|
|
alh1: alh1@24400 {
|
|
compatible = "intel,alh-dai";
|
|
reg = <0x00024400 0x00024600>;
|
|
status = "okay";
|
|
};
|
|
|
|
alh2: alh2@24400 {
|
|
compatible = "intel,alh-dai";
|
|
reg = <0x00024400 0x00024600>;
|
|
status = "okay";
|
|
};
|
|
|
|
alh3: alh3@24400 {
|
|
compatible = "intel,alh-dai";
|
|
reg = <0x00024400 0x00024600>;
|
|
status = "okay";
|
|
};
|
|
|
|
alh4: alh4@24400 {
|
|
compatible = "intel,alh-dai";
|
|
reg = <0x00024400 0x00024600>;
|
|
status = "okay";
|
|
};
|
|
|
|
alh5: alh5@24400 {
|
|
compatible = "intel,alh-dai";
|
|
reg = <0x00024400 0x00024600>;
|
|
status = "okay";
|
|
};
|
|
|
|
alh6: alh6@24400 {
|
|
compatible = "intel,alh-dai";
|
|
reg = <0x00024400 0x00024600>;
|
|
status = "okay";
|
|
};
|
|
|
|
alh7: alh7@24400 {
|
|
compatible = "intel,alh-dai";
|
|
reg = <0x00024400 0x00024600>;
|
|
status = "okay";
|
|
};
|
|
|
|
alh8: alh8@24400 {
|
|
compatible = "intel,alh-dai";
|
|
reg = <0x00024400 0x00024600>;
|
|
status = "okay";
|
|
};
|
|
|
|
alh9: alh9@24400 {
|
|
compatible = "intel,alh-dai";
|
|
reg = <0x00024400 0x00024600>;
|
|
status = "okay";
|
|
};
|
|
|
|
alh10: alh10@24400 {
|
|
compatible = "intel,alh-dai";
|
|
reg = <0x00024400 0x00024600>;
|
|
status = "okay";
|
|
};
|
|
|
|
alh11: alh11@24400 {
|
|
compatible = "intel,alh-dai";
|
|
reg = <0x00024400 0x00024600>;
|
|
status = "okay";
|
|
};
|
|
|
|
alh12: alh12@24400 {
|
|
compatible = "intel,alh-dai";
|
|
reg = <0x00024400 0x00024600>;
|
|
status = "okay";
|
|
};
|
|
|
|
alh13: alh13@24400 {
|
|
compatible = "intel,alh-dai";
|
|
reg = <0x00024400 0x00024600>;
|
|
status = "okay";
|
|
};
|
|
|
|
alh14: alh14@24400 {
|
|
compatible = "intel,alh-dai";
|
|
reg = <0x00024400 0x00024600>;
|
|
status = "okay";
|
|
};
|
|
|
|
alh15: alh15@24400 {
|
|
compatible = "intel,alh-dai";
|
|
reg = <0x00024400 0x00024600>;
|
|
status = "okay";
|
|
};
|
|
|
|
sspbase: ssp_base@28800 {
|
|
compatible = "intel,ssp-sspbase";
|
|
reg = <0x28800 0x1000>;
|
|
};
|
|
|
|
ssp0: ssp@28000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "intel,ssp";
|
|
reg = <0x00028000 0x1000
|
|
0x00079C00 0x200>;
|
|
interrupts = <0x00 0 0>;
|
|
interrupt-parent = <&ace_intc>;
|
|
dmas = <&lpgpdma0 2
|
|
&lpgpdma0 3>;
|
|
dma-names = "tx", "rx";
|
|
power-domain = <&io0_domain>;
|
|
ssp-index = <0>;
|
|
status = "okay";
|
|
|
|
ssp00: ssp@0 {
|
|
compatible = "intel,ssp-dai";
|
|
status = "okay";
|
|
reg = <0x0>;
|
|
};
|
|
};
|
|
|
|
ssp1: ssp@29000 {
|
|
compatible = "intel,ssp";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x00029000 0x1000
|
|
0x00079C00 0x200>;
|
|
interrupts = <0x01 0 0>;
|
|
interrupt-parent = <&ace_intc>;
|
|
dmas = <&lpgpdma0 4
|
|
&lpgpdma0 5>;
|
|
dma-names = "tx", "rx";
|
|
power-domain = <&io0_domain>;
|
|
ssp-index = <1>;
|
|
status = "okay";
|
|
|
|
ssp10: ssp@10 {
|
|
compatible = "intel,ssp-dai";
|
|
status = "okay";
|
|
reg = <0x10>;
|
|
};
|
|
};
|
|
|
|
ssp2: ssp@2a000 {
|
|
compatible = "intel,ssp";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x0002a000 0x1000
|
|
0x00079C00 0x200>;
|
|
interrupts = <0x02 0 0>;
|
|
interrupt-parent = <&ace_intc>;
|
|
dmas = <&lpgpdma0 6
|
|
&lpgpdma0 7>;
|
|
dma-names = "tx", "rx";
|
|
power-domain = <&io0_domain>;
|
|
ssp-index = <2>;
|
|
status = "okay";
|
|
|
|
ssp20: ssp@20 {
|
|
compatible = "intel,ssp-dai";
|
|
status = "okay";
|
|
reg = <0x20>;
|
|
};
|
|
};
|
|
|
|
mem_window0: mem_window@70200 {
|
|
compatible = "intel,adsp-mem-window";
|
|
reg = <0x70200 0x8>;
|
|
offset = <0x4000>;
|
|
memory = <&sram0>;
|
|
initialize;
|
|
read-only;
|
|
};
|
|
|
|
mem_window1: mem_window@70208 {
|
|
compatible = "intel,adsp-mem-window";
|
|
reg = <0x70208 0x8>;
|
|
memory = <&sram0>;
|
|
};
|
|
|
|
mem_window2: mem_window@70210 {
|
|
compatible = "intel,adsp-mem-window";
|
|
reg = <0x70210 0x8>;
|
|
memory = <&sram0>;
|
|
};
|
|
|
|
mem_window3: mem_window@70218 {
|
|
compatible = "intel,adsp-mem-window";
|
|
reg = <0x70218 0x8>;
|
|
memory = <&sram0>;
|
|
read-only;
|
|
};
|
|
|
|
adsp_idc: ace_idc@70400 {
|
|
compatible = "intel,adsp-idc";
|
|
reg = <0x70400 0x0400>;
|
|
interrupts = <24 0 0>;
|
|
interrupt-parent = <&ace_intc>;
|
|
};
|
|
|
|
dfpmcch: dfpmcch@71ac0 {
|
|
compatible = "intel,adsp-dfpmcch";
|
|
reg = <0x00071ac0 0x40>;
|
|
};
|
|
|
|
dfpmccu: dfpmccu@71b00 {
|
|
compatible = "intel,adsp-dfpmccu";
|
|
reg = <0x71b00 0x100>;
|
|
|
|
hub_ulp_domain: hub_ulp_domain {
|
|
compatible = "intel,adsp-power-domain";
|
|
bit-position = <15>;
|
|
};
|
|
ml1_domain: ml1_domain {
|
|
compatible = "intel,adsp-power-domain";
|
|
bit-position = <13>;
|
|
};
|
|
ml0_domain: ml0_domain {
|
|
compatible = "intel,adsp-power-domain";
|
|
bit-position = <12>;
|
|
};
|
|
io3_domain: io3_domain {
|
|
compatible = "intel,adsp-power-domain";
|
|
bit-position = <11>;
|
|
};
|
|
io2_domain: io2_domain {
|
|
compatible = "intel,adsp-power-domain";
|
|
bit-position = <10>;
|
|
};
|
|
io1_domain: io1_domain {
|
|
compatible = "intel,adsp-power-domain";
|
|
bit-position = <9>;
|
|
};
|
|
io0_domain: io0_domain {
|
|
compatible = "intel,adsp-power-domain";
|
|
bit-position = <8>;
|
|
};
|
|
hub_hp_domain: hub_hp_domain {
|
|
compatible = "intel,adsp-power-domain";
|
|
bit-position = <6>;
|
|
};
|
|
hst_domain: hst_domain {
|
|
compatible = "intel,adsp-power-domain";
|
|
bit-position = <4>;
|
|
};
|
|
};
|
|
|
|
ace_comm_widget: ace_comm_widget@71c00 {
|
|
compatible = "intel,adsp-communication-widget";
|
|
reg = <0x00071c00 0x100>;
|
|
interrupts = <0x19 0 0>;
|
|
interrupt-parent = <&ace_intc>;
|
|
status = "okay";
|
|
};
|
|
|
|
shim: shim@71f00 {
|
|
compatible = "intel,adsp-shim";
|
|
reg = <0x71f00 0x100>;
|
|
};
|
|
|
|
tts: tts@72000 {
|
|
compatible = "intel,adsp-tts";
|
|
reg = <0x72000 0x70>;
|
|
status = "okay";
|
|
};
|
|
|
|
ace_rtc_counter: ace_rtc_counter@72008 {
|
|
compatible = "intel,ace-rtc-counter";
|
|
reg = <0x72008 0x0064>;
|
|
};
|
|
|
|
ace_timestamp: ace_timestamp@72040 {
|
|
compatible = "intel,ace-timestamp";
|
|
reg = <0x72040 0x0032>;
|
|
};
|
|
|
|
ace_art_counter: ace_art_counter@72058 {
|
|
compatible = "intel,ace-art-counter";
|
|
reg = <0x72058 0x0064>;
|
|
};
|
|
|
|
hda_link_out: dma@72400 {
|
|
compatible = "intel,adsp-hda-link-out";
|
|
#dma-cells = <1>;
|
|
reg = <0x00072400 0x20>;
|
|
dma-channels = <9>;
|
|
dma-buf-addr-alignment = <128>;
|
|
dma-buf-size-alignment = <32>;
|
|
dma-copy-alignment = <16>;
|
|
power-domain = <&io0_domain>;
|
|
status = "okay";
|
|
};
|
|
|
|
hda_link_in: dma@72600 {
|
|
compatible = "intel,adsp-hda-link-in";
|
|
#dma-cells = <1>;
|
|
reg = <0x00072600 0x20>;
|
|
dma-channels = <10>;
|
|
dma-buf-addr-alignment = <128>;
|
|
dma-buf-size-alignment = <32>;
|
|
dma-copy-alignment = <16>;
|
|
power-domain = <&io0_domain>;
|
|
status = "okay";
|
|
};
|
|
|
|
hda_host_out: dma@72800 {
|
|
compatible = "intel,adsp-hda-host-out";
|
|
#dma-cells = <1>;
|
|
reg = <0x00072800 0x40>;
|
|
dma-channels = <9>;
|
|
dma-buf-addr-alignment = <128>;
|
|
dma-buf-size-alignment = <32>;
|
|
dma-copy-alignment = <16>;
|
|
power-domain = <&hst_domain>;
|
|
interrupts = <13 0 0>;
|
|
interrupt-parent = <&ace_intc>;
|
|
status = "okay";
|
|
};
|
|
|
|
hda_host_in: dma@72c00 {
|
|
compatible = "intel,adsp-hda-host-in";
|
|
#dma-cells = <1>;
|
|
reg = <0x00072c00 0x40>;
|
|
dma-channels = <10>;
|
|
dma-buf-addr-alignment = <128>;
|
|
dma-buf-size-alignment = <32>;
|
|
dma-copy-alignment = <16>;
|
|
power-domain = <&hst_domain>;
|
|
interrupts = <12 0 0>;
|
|
interrupt-parent = <&ace_intc>;
|
|
status = "okay";
|
|
};
|
|
|
|
adsp_host_ipc: ace_host_ipc@73000 {
|
|
compatible = "intel,adsp-host-ipc";
|
|
status = "okay";
|
|
reg = <0x73000 0x30>;
|
|
interrupts = <0 0 0>;
|
|
interrupt-parent = <&ace_intc>;
|
|
};
|
|
|
|
/* This is actually an array of per-core designware
|
|
* controllers, but the special setup and extra
|
|
* masking layer makes it easier for MTL to handle
|
|
* this internally.
|
|
*/
|
|
ace_intc: ace_intc@7ac00 {
|
|
compatible = "intel,ace-intc";
|
|
reg = <0x7ac00 0xc00>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
interrupts = <4 0 0>;
|
|
num-irqs = <28>;
|
|
interrupt-parent = <&core_intc>;
|
|
};
|
|
|
|
lpgpdma0: dma@7c000 {
|
|
compatible = "intel,adsp-gpdma";
|
|
#dma-cells = <1>;
|
|
reg = <0x0007c000 0x1000>;
|
|
shim = <0x0007c800 0x1000>;
|
|
interrupts = <17 0 0>;
|
|
interrupt-parent = <&ace_intc>;
|
|
dma-buf-size-alignment = <4>;
|
|
dma-copy-alignment = <4>;
|
|
status = "okay";
|
|
power-domain = <&hub_ulp_domain>;
|
|
zephyr,pm-device-runtime-auto;
|
|
};
|
|
|
|
lpgpdma1: dma@7d000 {
|
|
compatible = "intel,adsp-gpdma";
|
|
#dma-cells = <1>;
|
|
reg = <0x0007d000 0x1000>;
|
|
shim = <0x0007d800 0x1000>;
|
|
interrupts = <0x20 0 0>;
|
|
interrupt-parent = <&core_intc>;
|
|
dma-buf-size-alignment = <4>;
|
|
dma-copy-alignment = <4>;
|
|
status = "okay";
|
|
power-domain = <&io0_domain>;
|
|
zephyr,pm-device-runtime-auto;
|
|
};
|
|
|
|
lpgpdma2: dma@7e000 {
|
|
compatible = "intel,adsp-gpdma";
|
|
#dma-cells = <1>;
|
|
reg = <0x0007e000 0x1000>;
|
|
shim = <0x0007e800 0x1000>;
|
|
interrupts = <0x25 0 0>;
|
|
interrupt-parent = <&core_intc>;
|
|
dma-buf-size-alignment = <4>;
|
|
dma-copy-alignment = <4>;
|
|
power-domain = <&io0_domain>;
|
|
status = "okay";
|
|
zephyr,pm-device-runtime-auto;
|
|
};
|
|
|
|
sha: adsp-sha@17df00 {
|
|
compatible = "intel,adsp-sha";
|
|
reg = <0x17df00 0xd0>;
|
|
};
|
|
|
|
tlb: tlb@17e000 {
|
|
compatible = "intel,adsp-mtl-tlb";
|
|
reg = <0x17e000 0x1000>;
|
|
paddr-size = <12>;
|
|
exec-bit-idx = <14>;
|
|
write-bit-idx= <15>;
|
|
};
|
|
|
|
timer: timer {
|
|
compatible = "intel,adsp-timer";
|
|
syscon = <&tts>;
|
|
};
|
|
};
|
|
|
|
hdas {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
hda0: hda@0 {
|
|
compatible = "intel,hda-dai";
|
|
status = "okay";
|
|
reg = <0>;
|
|
};
|
|
hda1: hda@1 {
|
|
compatible = "intel,hda-dai";
|
|
status = "okay";
|
|
reg = <1>;
|
|
};
|
|
hda2: hda@2 {
|
|
compatible = "intel,hda-dai";
|
|
status = "okay";
|
|
reg = <2>;
|
|
};
|
|
hda3: hda@3 {
|
|
compatible = "intel,hda-dai";
|
|
status = "okay";
|
|
reg = <3>;
|
|
};
|
|
hda4: hda@4 {
|
|
compatible = "intel,hda-dai";
|
|
status = "okay";
|
|
reg = <4>;
|
|
};
|
|
hda5: hda@5 {
|
|
compatible = "intel,hda-dai";
|
|
status = "okay";
|
|
reg = <5>;
|
|
};
|
|
hda6: hda@6 {
|
|
compatible = "intel,hda-dai";
|
|
status = "okay";
|
|
reg = <6>;
|
|
};
|
|
hda7: hda@7 {
|
|
compatible = "intel,hda-dai";
|
|
status = "okay";
|
|
reg = <7>;
|
|
};
|
|
hda8: hda@8 {
|
|
compatible = "intel,hda-dai";
|
|
status = "okay";
|
|
reg = <8>;
|
|
};
|
|
hda9: hda@9 {
|
|
compatible = "intel,hda-dai";
|
|
status = "okay";
|
|
reg = <9>;
|
|
};
|
|
hda10: hda@a {
|
|
compatible = "intel,hda-dai";
|
|
status = "okay";
|
|
reg = <0x0a>;
|
|
};
|
|
hda11: hda@b {
|
|
compatible = "intel,hda-dai";
|
|
status = "okay";
|
|
reg = <0x0b>;
|
|
};
|
|
hda12: hda@c {
|
|
compatible = "intel,hda-dai";
|
|
status = "okay";
|
|
reg = <0x0c>;
|
|
};
|
|
hda13: hda@d {
|
|
compatible = "intel,hda-dai";
|
|
status = "okay";
|
|
reg = <0x0d>;
|
|
};
|
|
hda14: hda@e {
|
|
compatible = "intel,hda-dai";
|
|
status = "okay";
|
|
reg = <0x0e>;
|
|
};
|
|
hda15: hda@f {
|
|
compatible = "intel,hda-dai";
|
|
status = "okay";
|
|
reg = <0x0f>;
|
|
};
|
|
hda16: hda@10 {
|
|
compatible = "intel,hda-dai";
|
|
status = "okay";
|
|
reg = <0x10>;
|
|
};
|
|
hda17: hda@11 {
|
|
compatible = "intel,hda-dai";
|
|
status = "okay";
|
|
reg = <0x11>;
|
|
};
|
|
hda18: hda@12 {
|
|
compatible = "intel,hda-dai";
|
|
status = "okay";
|
|
reg = <0x12>;
|
|
};
|
|
};
|
|
};
|