17d9bea474
SOCs using the EDMA IP that supported caching must locate EDMA transfer control descriptors (TCDs) in non cacheable memory. For M7 cores, this can simply use the "nocache" section. For M4 cores, where the nocache section does not exist, the chosen SRAM section must be a tightly coupled memory block which cannot be cached. Add a note to all boards with M4 SOCs that support caching explaining this issue, and enable EDMA driver to locate TCDs in SRAM. Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com> |
||
|---|---|---|
| .. | ||
| doc | ||
| board.cmake | ||
| CMakeLists.txt | ||
| Kconfig.board | ||
| Kconfig.defconfig | ||
| rddrone_fmuk66-pinctrl.dtsi | ||
| rddrone_fmuk66.dts | ||
| rddrone_fmuk66.yaml | ||
| rddrone_fmuk66_defconfig | ||