zephyr/soc/sifive/sifive_freedom/fe300/Kconfig
Filip Kokosinski ab84989a12 arch/riscv: remove the Kconfig.core file
This commit removes the `Kconfig.core` file. It's been largely unused, and
the only symbol it provides (`RISCV_CORE_E31`) overlaps with the SoC-layer
provided `SOC_SERIES_SIFIVE_FREEDOM_FE300`.

As of date, the only SoC that uses the E31 core in Zephyr is the FE310 SoC.

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
2024-04-05 16:46:01 +03:00

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# Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
# Copyright (c) 2024 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_SIFIVE_FREEDOM_FE300
bool
# RISC-V options
select RISCV
select RISCV_PRIVILEGED
select RISCV_HAS_PLIC
select RISCV_PMP
select RISCV_ISA_RV32I
select RISCV_ISA_EXT_M
select RISCV_ISA_EXT_A
select RISCV_ISA_EXT_C
select RISCV_ISA_EXT_ZICSR
select RISCV_ISA_EXT_ZIFENCEI
select ATOMIC_OPERATIONS_C
select INCLUDE_RESET_VECTOR