zephyr/arch/common
Jiafei Pan 799f37b421 arm64: add nocache memory segment support
In some drivers, noncache memory need to be used for dma coherent
memroy, so add nocache memory segment mapping and support for ARM64
platforms.

The following variables definition example shows they will use nocache
memory allocation:
   int var1 __nocache;
   int var2 __attribute__((__section__(".nocache")));

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
2021-10-20 08:56:40 -05:00
..
CMakeLists.txt arch: linker: specify intList section in the IDT_LIST region 2021-08-30 08:54:23 -04:00
gen_isr_tables.py gen_isr_tables: Added check of the IRQ num before accessing the vt 2021-01-24 10:12:54 -05:00
isr_tables.c isr_tables: adopt _irq_vector_table for using on 64bit architectures 2021-01-04 16:47:51 -08:00
nocache.ld arm64: add nocache memory segment support 2021-10-20 08:56:40 -05:00
ramfunc.ld linker: align _ramfunc_ram/rom_start/size linker symbol names 2021-08-28 08:48:03 -04:00
rom_start_offset.ld config: Rename TEXT_SECTION_OFFSET to ROM_START_OFFSET 2020-07-09 14:02:38 -04:00
sw_isr_common.c arch: common: Fix 10.4 violations 2021-04-10 09:59:37 -04:00
timing.c arch: common: Fix 10.4 violations 2021-04-10 09:59:37 -04:00