178bdc4afc
Change automated searching for files using "IRQ_CONNECT()" API not including <zephyr/irq.h>. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
441 lines
10 KiB
C
441 lines
10 KiB
C
/*
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* Copyright (c) 2022 Andes Technology Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "spi_andes_atcspi200.h"
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#include <zephyr/irq.h>
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#define DT_DRV_COMPAT andestech_atcspi200
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typedef void (*atcspi200_cfg_func_t)(void);
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struct spi_atcspi200_data {
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struct spi_context ctx;
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uint32_t tx_fifo_size;
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uint32_t rx_fifo_size;
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int tx_cnt;
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uint32_t is_cmdaddr_mode;
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size_t chunk_len;
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bool busy;
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};
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struct spi_atcspi200_cfg {
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atcspi200_cfg_func_t cfg_func;
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uint32_t base;
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uint32_t irq_num;
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uint32_t f_sys;
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bool xip;
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};
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/* API Functions */
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static int spi_config(const struct device *dev,
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const struct spi_config *config)
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{
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const struct spi_atcspi200_cfg * const cfg = dev->config;
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uint32_t sclk_div, data_len;
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/* Set the divisor for SPI interface sclk */
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sclk_div = (cfg->f_sys / (config->frequency << 1)) - 1;
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CLR_MASK(SPI_TIMIN(dev), TIMIN_SCLK_DIV_MSK);
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SET_MASK(SPI_TIMIN(dev), sclk_div);
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/* Set Master mode */
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CLR_MASK(SPI_TFMAT(dev), TFMAT_SLVMODE_MSK);
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/* Disable data merge mode */
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CLR_MASK(SPI_TFMAT(dev), TFMAT_DATA_MERGE_MSK);
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/* Set data length */
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data_len = SPI_WORD_SIZE_GET(config->operation) - 1;
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CLR_MASK(SPI_TFMAT(dev), TFMAT_DATA_LEN_MSK);
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SET_MASK(SPI_TFMAT(dev), (data_len << TFMAT_DATA_LEN_OFFSET));
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/* Set SPI frame format */
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if (config->operation & SPI_MODE_CPHA) {
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SET_MASK(SPI_TFMAT(dev), TFMAT_CPHA_MSK);
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} else {
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CLR_MASK(SPI_TFMAT(dev), TFMAT_CPHA_MSK);
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}
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if (config->operation & SPI_MODE_CPOL) {
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SET_MASK(SPI_TFMAT(dev), TFMAT_CPOL_MSK);
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} else {
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CLR_MASK(SPI_TFMAT(dev), TFMAT_CPOL_MSK);
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}
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/* Set SPI bit order */
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if (config->operation & SPI_TRANSFER_LSB) {
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SET_MASK(SPI_TFMAT(dev), TFMAT_LSB_MSK);
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} else {
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CLR_MASK(SPI_TFMAT(dev), TFMAT_LSB_MSK);
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}
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/* Set TX/RX FIFO threshold */
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CLR_MASK(SPI_CTRL(dev), CTRL_TX_THRES_MSK);
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CLR_MASK(SPI_CTRL(dev), CTRL_RX_THRES_MSK);
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SET_MASK(SPI_CTRL(dev), TX_FIFO_THRESHOLD << CTRL_TX_THRES_OFFSET);
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SET_MASK(SPI_CTRL(dev), RX_FIFO_THRESHOLD << CTRL_RX_THRES_OFFSET);
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return 0;
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}
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static int spi_transfer(const struct device *dev, uint32_t len)
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{
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struct spi_atcspi200_data * const data = dev->data;
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struct spi_context *ctx = &data->ctx;
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uint32_t data_len, tctrl, int_msk;
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if (len > MAX_TRANSFER_CNT) {
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return -EINVAL;
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}
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data_len = len - 1;
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data->tx_cnt = 0;
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if (!spi_context_rx_on(ctx)) {
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tctrl = (TRNS_MODE_WRITE_ONLY << TCTRL_TRNS_MODE_OFFSET) |
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(data_len << TCTRL_WR_TCNT_OFFSET);
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int_msk = IEN_TX_FIFO_MSK | IEN_END_MSK;
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} else if (!spi_context_tx_on(ctx)) {
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tctrl = (TRNS_MODE_READ_ONLY << TCTRL_TRNS_MODE_OFFSET) |
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(data_len << TCTRL_RD_TCNT_OFFSET);
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int_msk = IEN_RX_FIFO_MSK | IEN_END_MSK;
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} else {
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tctrl = (TRNS_MODE_WRITE_READ << TCTRL_TRNS_MODE_OFFSET) |
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(data_len << TCTRL_WR_TCNT_OFFSET) |
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(data_len << TCTRL_RD_TCNT_OFFSET);
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int_msk = IEN_TX_FIFO_MSK |
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IEN_RX_FIFO_MSK |
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IEN_END_MSK;
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}
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sys_write32(tctrl, SPI_TCTRL(dev));
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/* Enable TX/RX FIFO interrupts */
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sys_write32(int_msk, SPI_INTEN(dev));
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if (!data->is_cmdaddr_mode) {
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/* Start transferring */
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sys_write32(0, SPI_CMD(dev));
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}
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return 0;
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}
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static int configure(const struct device *dev,
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const struct spi_config *config)
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{
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struct spi_atcspi200_data * const data = dev->data;
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struct spi_context *ctx = &(data->ctx);
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if (spi_context_configured(ctx, config)) {
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/* Already configured. No need to do it again. */
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return 0;
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}
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if (SPI_OP_MODE_GET(config->operation) != SPI_OP_MODE_MASTER) {
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LOG_ERR("Slave mode is not supported on %s",
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dev->name);
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return -EINVAL;
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}
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if (config->operation & SPI_MODE_LOOP) {
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LOG_ERR("Loopback mode is not supported");
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return -EINVAL;
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}
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if ((config->operation & SPI_LINES_MASK) != SPI_LINES_SINGLE) {
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LOG_ERR("Only single line mode is supported");
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return -EINVAL;
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}
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ctx->config = config;
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/* SPI configuration */
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spi_config(dev, config);
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return 0;
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}
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static void transfer_next_chunk(const struct device *dev)
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{
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struct spi_atcspi200_data * const data = dev->data;
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struct spi_context *ctx = &data->ctx;
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int error = 0;
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size_t chunk_len = spi_context_max_continuous_chunk(ctx);
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if (chunk_len > 0) {
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data->chunk_len = chunk_len;
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error = spi_transfer(dev, chunk_len);
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if (error == 0) {
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return;
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}
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}
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spi_context_cs_control(ctx, false);
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/* Reset TX/RX FIFO */
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SET_MASK(SPI_CTRL(dev), CTRL_TX_FIFO_RST_MSK);
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SET_MASK(SPI_CTRL(dev), CTRL_RX_FIFO_RST_MSK);
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spi_context_complete(ctx, dev, error);
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data->busy = false;
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}
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static int transceive(const struct device *dev,
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const struct spi_config *config,
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const struct spi_buf_set *tx_bufs,
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const struct spi_buf_set *rx_bufs,
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bool asynchronous,
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spi_callback_t cb,
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void *userdata)
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{
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struct spi_atcspi200_data * const data = dev->data;
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struct spi_context *ctx = &data->ctx;
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int error, dfs;
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spi_context_lock(ctx, asynchronous, cb, userdata, config);
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error = configure(dev, config);
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if (error == 0) {
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data->busy = true;
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dfs = SPI_WORD_SIZE_GET(ctx->config->operation) >> 3;
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spi_context_buffers_setup(ctx, tx_bufs, rx_bufs, dfs);
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spi_context_cs_control(ctx, true);
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transfer_next_chunk(dev);
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error = spi_context_wait_for_completion(ctx);
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}
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spi_context_release(ctx, error);
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return error;
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}
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int spi_atcspi200_transceive(const struct device *dev,
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const struct spi_config *config,
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const struct spi_buf_set *tx_bufs,
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const struct spi_buf_set *rx_bufs)
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{
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return transceive(dev, config, tx_bufs, rx_bufs, false, NULL, NULL);
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}
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#ifdef CONFIG_SPI_ASYNC
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int spi_atcspi200_transceive_async(const struct device *dev,
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const struct spi_config *config,
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const struct spi_buf_set *tx_bufs,
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const struct spi_buf_set *rx_bufs,
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spi_callback_t cb,
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void *userdata)
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{
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return transceive(dev, config, tx_bufs, rx_bufs, true, cb, userdata);
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}
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#endif
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int spi_atcspi200_release(const struct device *dev,
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const struct spi_config *config)
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{
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struct spi_atcspi200_data * const data = dev->data;
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if (data->busy) {
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return -EBUSY;
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}
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spi_context_unlock_unconditionally(&data->ctx);
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return 0;
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}
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int spi_atcspi200_init(const struct device *dev)
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{
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const struct spi_atcspi200_cfg * const cfg = dev->config;
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struct spi_atcspi200_data * const data = dev->data;
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int err = 0;
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/* we should not configure the device we are running on */
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if (cfg->xip) {
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return -EINVAL;
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}
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spi_context_unlock_unconditionally(&data->ctx);
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/* Get the TX/RX FIFO size of this device */
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data->tx_fifo_size = TX_FIFO_SIZE(dev);
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data->rx_fifo_size = RX_FIFO_SIZE(dev);
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cfg->cfg_func();
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irq_enable(cfg->irq_num);
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err = spi_context_cs_configure_all(&data->ctx);
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if (err < 0) {
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return err;
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}
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return 0;
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}
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static struct spi_driver_api spi_atcspi200_api = {
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.transceive = spi_atcspi200_transceive,
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#ifdef CONFIG_SPI_ASYNC
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.transceive_async = spi_atcspi200_transceive_async,
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#endif
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.release = spi_atcspi200_release
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};
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static void spi_atcspi200_irq_handler(void *arg)
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{
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const struct device * const dev = (const struct device *) arg;
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struct spi_atcspi200_data * const data = dev->data;
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struct spi_context *ctx = &data->ctx;
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uint32_t rx_data, cur_tx_fifo_num, cur_rx_fifo_num;
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uint32_t i, dfs, intr_status, spi_status;
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uint32_t tx_num = 0, tx_data = 0;
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intr_status = sys_read32(SPI_INTST(dev));
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dfs = SPI_WORD_SIZE_GET(ctx->config->operation) >> 3;
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if ((intr_status & INTST_TX_FIFO_INT_MSK) &&
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!(intr_status & INTST_END_INT_MSK)) {
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spi_status = sys_read32(SPI_STAT(dev));
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cur_tx_fifo_num = GET_TX_NUM(dev);
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tx_num = data->tx_fifo_size - cur_tx_fifo_num;
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for (i = tx_num; i > 0; i--) {
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if (data->tx_cnt >= data->chunk_len) {
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/* Have already sent a chunk of data, so stop
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* sending data!
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*/
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CLR_MASK(SPI_INTEN(dev), IEN_TX_FIFO_MSK);
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break;
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}
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if (spi_context_tx_buf_on(ctx)) {
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switch (dfs) {
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case 1:
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tx_data = *ctx->tx_buf;
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break;
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case 2:
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tx_data = *(uint16_t *)ctx->tx_buf;
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break;
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}
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} else if (spi_context_tx_on(ctx)) {
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tx_data = 0;
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} else {
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CLR_MASK(SPI_INTEN(dev), IEN_TX_FIFO_MSK);
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break;
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}
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sys_write32(tx_data, SPI_DATA(dev));
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spi_context_update_tx(ctx, dfs, 1);
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data->tx_cnt++;
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}
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sys_write32(INTST_TX_FIFO_INT_MSK, SPI_INTST(dev));
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}
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if (intr_status & INTST_RX_FIFO_INT_MSK) {
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cur_rx_fifo_num = GET_RX_NUM(dev);
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for (i = cur_rx_fifo_num; i > 0; i--) {
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rx_data = sys_read32(SPI_DATA(dev));
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if (spi_context_rx_buf_on(ctx)) {
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switch (dfs) {
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case 1:
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*ctx->rx_buf = rx_data;
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break;
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case 2:
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*(uint16_t *)ctx->rx_buf = rx_data;
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break;
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}
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} else if (!spi_context_rx_on(ctx)) {
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CLR_MASK(SPI_INTEN(dev), IEN_RX_FIFO_MSK);
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}
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spi_context_update_rx(ctx, dfs, 1);
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}
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sys_write32(INTST_RX_FIFO_INT_MSK, SPI_INTST(dev));
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}
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if (intr_status & INTST_END_INT_MSK) {
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/* Clear end interrupt */
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sys_write32(INTST_END_INT_MSK, SPI_INTST(dev));
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/* Disable all SPI interrupts */
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sys_write32(0, SPI_INTEN(dev));
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transfer_next_chunk(dev);
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}
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}
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#define SPI_DMA_CHANNEL(id, dir, DIR, src, dest)
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#define SPI_IF_NO_CMD(num) .is_cmdaddr_mode = 0,
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#define SPI_BUSY_INIT .busy = false,
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#if (CONFIG_XIP)
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#define SPI_ROM_CFG_XIP(node_id) DT_SAME_NODE(node_id, DT_BUS(DT_CHOSEN(zephyr_flash)))
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#else
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#define SPI_ROM_CFG_XIP(node_id) false
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#endif
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#define SPI_INIT(n) \
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static struct spi_atcspi200_data spi_atcspi200_dev_data_##n = { \
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SPI_CONTEXT_INIT_LOCK(spi_atcspi200_dev_data_##n, ctx), \
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SPI_CONTEXT_INIT_SYNC(spi_atcspi200_dev_data_##n, ctx), \
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SPI_CONTEXT_CS_GPIOS_INITIALIZE(DT_DRV_INST(n), ctx) \
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SPI_IF_NO_CMD(n) \
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SPI_BUSY_INIT \
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SPI_DMA_CHANNEL(n, rx, RX, PERIPHERAL, MEMORY) \
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SPI_DMA_CHANNEL(n, tx, TX, MEMORY, PERIPHERAL) \
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}; \
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static void spi_atcspi200_cfg_##n(void); \
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static const struct spi_atcspi200_cfg spi_atcspi200_dev_cfg_##n = { \
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.cfg_func = spi_atcspi200_cfg_##n, \
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.base = DT_INST_REG_ADDR(n), \
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.irq_num = DT_INST_IRQN(n), \
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.f_sys = DT_INST_PROP(n, clock_frequency), \
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.xip = SPI_ROM_CFG_XIP(DT_DRV_INST(n)), \
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}; \
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\
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DEVICE_DT_INST_DEFINE(n, \
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spi_atcspi200_init, \
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NULL, \
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&spi_atcspi200_dev_data_##n, \
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&spi_atcspi200_dev_cfg_##n, \
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POST_KERNEL, \
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CONFIG_SPI_INIT_PRIORITY, \
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&spi_atcspi200_api); \
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\
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static void spi_atcspi200_cfg_##n(void) \
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{ \
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\
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IRQ_CONNECT(DT_INST_IRQN(n), \
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DT_INST_IRQ(n, priority), \
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spi_atcspi200_irq_handler, \
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DEVICE_DT_INST_GET(n), \
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0); \
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\
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}
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DT_INST_FOREACH_STATUS_OKAY(SPI_INIT)
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