zephyr/soc/xtensa
Daniel Leung 9fc99928ca soc: intel_adsp/ace: update SOC_TOOLCHAIN_NAME
Update the SOC_TOOLCHAIN_NAME to intel_ace15_mtpm so that
we use the correct overlay in Xtensa HAL module. Note that
ace20_lnl will also be using this as well. That will change
once we have a proper toolchain for ace20_lnl.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2023-05-16 01:50:00 +09:00
..
esp32 xtensa: add some structs for interrupt stack frames 2023-04-20 04:45:52 -04:00
esp32_net soc: kconfig: Add config for ESP32 family 2023-04-19 17:12:26 +02:00
esp32s2 soc: kconfig: Add config for ESP32 family 2023-04-19 17:12:26 +02:00
esp32s3 drivers: flash: esp32s3: Add spiflash support 2023-04-28 10:08:16 +02:00
intel_adsp soc: intel_adsp/ace: update SOC_TOOLCHAIN_NAME 2023-05-16 01:50:00 +09:00
nxp_adsp boards: xtensa: nxp_adsp_imx8m: Add UART support for the ADSP from i.MX8MP 2023-05-08 13:06:12 -05:00
sample_controller xtensa: linker: Use zephyr's convention for rodata 2022-11-17 15:44:48 +09:00
CMakeLists.txt soc/xtensa/intel_adsp: Upstream updates 2020-10-21 06:38:53 -04:00