3ffcd75469
This change marks each instance of the 'spi_driver_api' as 'static const'. The rationale is that 'spi_driver_api' is used for declaring internal module interfaces and is not intended to be modified at runtime. By using 'static const', we ensure immutability, leading to usage of only .rodata and a reduction in the .data area. Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
384 lines
11 KiB
C
384 lines
11 KiB
C
/*
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* Copyright (c) 2023 Stephen Boylan <stephen.boylan@beechwoods.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT raspberrypi_pico_spi_pio
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#define LOG_LEVEL CONFIG_SPI_LOG_LEVEL
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(spi_pico_pio);
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#include <zephyr/sys/util.h>
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#include <zephyr/sys/sys_io.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/drivers/spi.h>
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#include <zephyr/drivers/pinctrl.h>
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#include "spi_context.h"
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#include <zephyr/drivers/misc/pio_rpi_pico/pio_rpi_pico.h>
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#include <hardware/pio.h>
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#include "hardware/clocks.h"
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#define PIO_CYCLES (4)
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#define PIO_FIFO_DEPTH (4)
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struct spi_pico_pio_config {
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const struct device *piodev;
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const struct pinctrl_dev_config *pin_cfg;
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struct gpio_dt_spec clk_gpio;
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struct gpio_dt_spec mosi_gpio;
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struct gpio_dt_spec miso_gpio;
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const struct device *clk_dev;
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clock_control_subsys_t clk_id;
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};
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struct spi_pico_pio_data {
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struct spi_context spi_ctx;
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uint32_t tx_count;
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uint32_t rx_count;
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PIO pio;
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size_t pio_sm;
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uint32_t dfs;
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};
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RPI_PICO_PIO_DEFINE_PROGRAM(spi_cpol_0_cpha_0, 0, 1,
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/* .wrap_target */
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0x6101, /* 0: out pins, 1 side 0 [1] */
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0x5101, /* 1: in pins, 1 side 1 [1] */
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/* .wrap */
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);
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RPI_PICO_PIO_DEFINE_PROGRAM(spi_cpol_1_cpha_1, 0, 2,
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/* .wrap_target */
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0x7021, /* 0: out x, 1 side 1 */
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0xa101, /* 1: mov pins, x side 0 [1] */
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0x5001, /* 2: in pins, 1 side 1 */
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/* .wrap */
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);
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static float spi_pico_pio_clock_divisor(const uint32_t clock_freq, uint32_t spi_frequency)
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{
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return (float)clock_freq / (float)(PIO_CYCLES * spi_frequency);
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}
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static uint32_t spi_pico_pio_maximum_clock_frequency(const uint32_t clock_freq)
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{
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return clock_freq / PIO_CYCLES;
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}
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static uint32_t spi_pico_pio_minimum_clock_frequency(const uint32_t clock_freq)
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{
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return clock_freq / (PIO_CYCLES * 65536);
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}
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static inline bool spi_pico_pio_transfer_ongoing(struct spi_pico_pio_data *data)
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{
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return spi_context_tx_on(&data->spi_ctx) || spi_context_rx_on(&data->spi_ctx);
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}
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static inline void spi_pico_pio_sm_put8(PIO pio, uint sm, uint8_t data)
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{
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/* Do 8 bit accesses on FIFO, so that write data is byte-replicated. This */
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/* gets us the left-justification for free (for MSB-first shift-out) */
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io_rw_8 *txfifo = (io_rw_8 *)&pio->txf[sm];
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*txfifo = data;
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}
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static inline uint8_t spi_pico_pio_sm_get8(PIO pio, uint sm)
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{
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/* Do 8 bit accesses on FIFO, so that write data is byte-replicated. This */
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/* gets us the left-justification for free (for MSB-first shift-out) */
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io_rw_8 *rxfifo = (io_rw_8 *)&pio->rxf[sm];
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return *rxfifo;
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}
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static int spi_pico_pio_configure(const struct spi_pico_pio_config *dev_cfg,
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struct spi_pico_pio_data *data, const struct spi_config *spi_cfg)
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{
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const struct gpio_dt_spec *miso;
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const struct gpio_dt_spec *mosi;
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const struct gpio_dt_spec *clk;
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pio_sm_config sm_config;
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uint32_t offset;
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uint32_t wrap_target;
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uint32_t wrap;
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uint32_t cpol = 0;
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uint32_t cpha = 0;
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uint32_t bits;
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uint32_t clock_freq;
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float clock_div;
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const pio_program_t *program;
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int rc;
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rc = clock_control_on(dev_cfg->clk_dev, dev_cfg->clk_id);
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if (rc < 0) {
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LOG_ERR("Failed to enable the clock");
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return rc;
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}
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rc = clock_control_get_rate(dev_cfg->clk_dev, dev_cfg->clk_id, &clock_freq);
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if (rc < 0) {
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LOG_ERR("Failed to get clock frequency");
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return rc;
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}
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if (spi_context_configured(&data->spi_ctx, spi_cfg)) {
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return 0;
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}
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if (spi_cfg->operation & SPI_OP_MODE_SLAVE) {
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LOG_ERR("Slave mode not supported");
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return -ENOTSUP;
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}
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if (spi_cfg->operation & SPI_TRANSFER_LSB) {
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LOG_ERR("Unsupported configuration");
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return -ENOTSUP;
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}
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#if defined(CONFIG_SPI_EXTENDED_MODES)
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if (spi_cfg->operation & (SPI_LINES_DUAL | SPI_LINES_QUAD | SPI_LINES_OCTAL)) {
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LOG_ERR("Unsupported configuration");
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return -ENOTSUP;
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}
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#endif /* CONFIG_SPI_EXTENDED_MODES */
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bits = SPI_WORD_SIZE_GET(spi_cfg->operation);
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if (bits != 8) {
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LOG_ERR("Only 8 bit word size is supported");
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return -ENOTSUP;
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}
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data->dfs = DIV_ROUND_UP(bits, 8);
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if ((spi_cfg->frequency < spi_pico_pio_minimum_clock_frequency(clock_freq)) ||
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(spi_cfg->frequency > spi_pico_pio_maximum_clock_frequency(clock_freq))) {
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LOG_ERR("clock-frequency out of range");
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return -EINVAL;
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}
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clock_div = spi_pico_pio_clock_divisor(clock_freq, spi_cfg->frequency);
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/* Half-duplex mode has not been implemented */
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if (spi_cfg->operation & SPI_HALF_DUPLEX) {
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LOG_ERR("Half-duplex not supported");
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return -ENOTSUP;
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}
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if (SPI_MODE_GET(spi_cfg->operation) & SPI_MODE_CPOL) {
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cpol = 1;
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}
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if (SPI_MODE_GET(spi_cfg->operation) & SPI_MODE_CPHA) {
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cpha = 1;
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}
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if (SPI_MODE_GET(spi_cfg->operation) & SPI_MODE_LOOP) {
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LOG_ERR("Loopback not supported");
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return -ENOTSUP;
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}
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mosi = &dev_cfg->mosi_gpio;
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miso = &dev_cfg->miso_gpio;
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clk = &dev_cfg->clk_gpio;
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data->pio = pio_rpi_pico_get_pio(dev_cfg->piodev);
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rc = pio_rpi_pico_allocate_sm(dev_cfg->piodev, &data->pio_sm);
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if (rc < 0) {
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return rc;
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}
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if ((cpol == 0) && (cpha == 0)) {
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program = RPI_PICO_PIO_GET_PROGRAM(spi_cpol_0_cpha_0);
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wrap_target = RPI_PICO_PIO_GET_WRAP_TARGET(spi_cpol_0_cpha_0);
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wrap = RPI_PICO_PIO_GET_WRAP(spi_cpol_0_cpha_0);
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} else if ((cpol == 1) && (cpha == 1)) {
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program = RPI_PICO_PIO_GET_PROGRAM(spi_cpol_1_cpha_1);
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wrap_target = RPI_PICO_PIO_GET_WRAP_TARGET(spi_cpol_1_cpha_1);
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wrap = RPI_PICO_PIO_GET_WRAP(spi_cpol_1_cpha_1);
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} else {
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LOG_ERR("Not supported: cpol=%d, cpha=%d\n", cpol, cpha);
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return -ENOTSUP;
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}
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if (!pio_can_add_program(data->pio, program)) {
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return -EBUSY;
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}
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offset = pio_add_program(data->pio, program);
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sm_config = pio_get_default_sm_config();
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sm_config_set_clkdiv(&sm_config, clock_div);
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sm_config_set_in_pins(&sm_config, miso->pin);
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sm_config_set_in_shift(&sm_config, false, true, bits);
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sm_config_set_out_pins(&sm_config, mosi->pin, 1);
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sm_config_set_out_shift(&sm_config, false, true, bits);
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sm_config_set_sideset_pins(&sm_config, clk->pin);
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sm_config_set_sideset(&sm_config, 1, false, false);
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sm_config_set_wrap(&sm_config, offset + wrap_target, offset + wrap);
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pio_sm_set_consecutive_pindirs(data->pio, data->pio_sm, miso->pin, 1, false);
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pio_sm_set_pindirs_with_mask(data->pio, data->pio_sm, (BIT(clk->pin) | BIT(mosi->pin)),
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(BIT(clk->pin) | BIT(mosi->pin)));
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pio_sm_set_pins_with_mask(data->pio, data->pio_sm, (cpol << clk->pin),
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BIT(clk->pin) | BIT(mosi->pin));
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pio_gpio_init(data->pio, mosi->pin);
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pio_gpio_init(data->pio, miso->pin);
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pio_gpio_init(data->pio, clk->pin);
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pio_sm_init(data->pio, data->pio_sm, offset, &sm_config);
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pio_sm_set_enabled(data->pio, data->pio_sm, true);
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data->spi_ctx.config = spi_cfg;
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return 0;
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}
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static void spi_pico_pio_txrx(const struct device *dev)
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{
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struct spi_pico_pio_data *data = dev->data;
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const size_t chunk_len = spi_context_max_continuous_chunk(&data->spi_ctx);
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const void *txbuf = data->spi_ctx.tx_buf;
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void *rxbuf = data->spi_ctx.rx_buf;
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uint32_t txrx;
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size_t fifo_cnt = 0;
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data->tx_count = 0;
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data->rx_count = 0;
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pio_sm_clear_fifos(data->pio, data->pio_sm);
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while (data->rx_count < chunk_len || data->tx_count < chunk_len) {
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/* Fill up fifo with available TX data */
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while ((!pio_sm_is_tx_fifo_full(data->pio, data->pio_sm)) &&
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data->tx_count < chunk_len && fifo_cnt < PIO_FIFO_DEPTH) {
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/* Send 0 in the case of read only operation */
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txrx = 0;
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if (txbuf) {
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txrx = ((uint8_t *)txbuf)[data->tx_count];
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}
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spi_pico_pio_sm_put8(data->pio, data->pio_sm, txrx);
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data->tx_count++;
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fifo_cnt++;
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}
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while ((!pio_sm_is_rx_fifo_empty(data->pio, data->pio_sm)) &&
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data->rx_count < chunk_len && fifo_cnt > 0) {
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txrx = spi_pico_pio_sm_get8(data->pio, data->pio_sm);
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/* Discard received data if rx buffer not assigned */
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if (rxbuf) {
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((uint8_t *)rxbuf)[data->rx_count] = (uint8_t)txrx;
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}
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data->rx_count++;
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fifo_cnt--;
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}
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}
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}
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static int spi_pico_pio_transceive_impl(const struct device *dev, const struct spi_config *spi_cfg,
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const struct spi_buf_set *tx_bufs,
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const struct spi_buf_set *rx_bufs, bool asynchronous,
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spi_callback_t cb, void *userdata)
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{
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const struct spi_pico_pio_config *dev_cfg = dev->config;
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struct spi_pico_pio_data *data = dev->data;
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struct spi_context *spi_ctx = &data->spi_ctx;
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int rc = 0;
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spi_context_lock(spi_ctx, asynchronous, cb, userdata, spi_cfg);
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rc = spi_pico_pio_configure(dev_cfg, data, spi_cfg);
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if (rc < 0) {
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goto error;
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}
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spi_context_buffers_setup(spi_ctx, tx_bufs, rx_bufs, data->dfs);
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spi_context_cs_control(spi_ctx, true);
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do {
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spi_pico_pio_txrx(dev);
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spi_context_update_tx(spi_ctx, 1, data->tx_count);
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spi_context_update_rx(spi_ctx, 1, data->rx_count);
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} while (spi_pico_pio_transfer_ongoing(data));
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spi_context_cs_control(spi_ctx, false);
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error:
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spi_context_release(spi_ctx, rc);
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return rc;
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}
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static int spi_pico_pio_transceive(const struct device *dev, const struct spi_config *spi_cfg,
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const struct spi_buf_set *tx_bufs,
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const struct spi_buf_set *rx_bufs)
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{
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return spi_pico_pio_transceive_impl(dev, spi_cfg, tx_bufs, rx_bufs, false, NULL, NULL);
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}
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int spi_pico_pio_release(const struct device *dev, const struct spi_config *spi_cfg)
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{
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struct spi_pico_pio_data *data = dev->data;
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spi_context_unlock_unconditionally(&data->spi_ctx);
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return 0;
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}
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static const struct spi_driver_api spi_pico_pio_api = {
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.transceive = spi_pico_pio_transceive,
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.release = spi_pico_pio_release,
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};
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int spi_pico_pio_init(const struct device *dev)
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{
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const struct spi_pico_pio_config *dev_cfg = dev->config;
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struct spi_pico_pio_data *data = dev->data;
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int rc;
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rc = pinctrl_apply_state(dev_cfg->pin_cfg, PINCTRL_STATE_DEFAULT);
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if (rc) {
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LOG_ERR("Failed to apply pinctrl state");
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return rc;
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}
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rc = spi_context_cs_configure_all(&data->spi_ctx);
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if (rc < 0) {
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LOG_ERR("Failed to configure CS pins: %d", rc);
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return rc;
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}
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spi_context_unlock_unconditionally(&data->spi_ctx);
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return 0;
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}
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#define SPI_PICO_PIO_INIT(inst) \
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PINCTRL_DT_INST_DEFINE(inst); \
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static struct spi_pico_pio_config spi_pico_pio_config_##inst = { \
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.piodev = DEVICE_DT_GET(DT_INST_PARENT(inst)), \
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.pin_cfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
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.clk_gpio = GPIO_DT_SPEC_INST_GET(inst, clk_gpios), \
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.mosi_gpio = GPIO_DT_SPEC_INST_GET_OR(inst, mosi_gpios, {0}), \
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.miso_gpio = GPIO_DT_SPEC_INST_GET_OR(inst, miso_gpios, {0}), \
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.clk_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(inst)), \
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.clk_id = (clock_control_subsys_t)DT_INST_PHA_BY_IDX(inst, clocks, 0, clk_id), \
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}; \
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static struct spi_pico_pio_data spi_pico_pio_data_##inst = { \
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SPI_CONTEXT_INIT_LOCK(spi_pico_pio_data_##inst, spi_ctx), \
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SPI_CONTEXT_INIT_SYNC(spi_pico_pio_data_##inst, spi_ctx), \
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SPI_CONTEXT_CS_GPIOS_INITIALIZE(DT_DRV_INST(inst), spi_ctx)}; \
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DEVICE_DT_INST_DEFINE(inst, spi_pico_pio_init, NULL, &spi_pico_pio_data_##inst, \
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&spi_pico_pio_config_##inst, POST_KERNEL, CONFIG_SPI_INIT_PRIORITY, \
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&spi_pico_pio_api); \
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BUILD_ASSERT(DT_INST_NODE_HAS_PROP(inst, clk_gpios)); \
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BUILD_ASSERT(DT_INST_NODE_HAS_PROP(inst, mosi_gpios)); \
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BUILD_ASSERT(DT_INST_NODE_HAS_PROP(inst, miso_gpios));
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DT_INST_FOREACH_STATUS_OKAY(SPI_PICO_PIO_INIT)
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