393 lines
13 KiB
C
393 lines
13 KiB
C
/*
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* Copyright (c) 2020 Linumiz
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* Author: Parthiban Nallathambi <parthiban@linumiz.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT infineon_xmc4xxx_uart
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#include <xmc_uart.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/drivers/uart.h>
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#include <zephyr/sys/util.h>
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struct uart_xmc4xxx_config {
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XMC_USIC_CH_t *uart;
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const struct pinctrl_dev_config *pcfg;
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uint8_t input_src;
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#if defined(CONFIG_UART_INTERRUPT_DRIVEN)
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uart_irq_config_func_t irq_config_func;
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uint8_t irq_num;
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#endif
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uint8_t fifo_start_offset;
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uint8_t fifo_tx_size;
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uint8_t fifo_rx_size;
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};
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struct uart_xmc4xxx_data {
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XMC_UART_CH_CONFIG_t config;
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#if defined(CONFIG_UART_INTERRUPT_DRIVEN)
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uart_irq_callback_user_data_t user_cb;
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void *user_data;
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uint8_t service_request;
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#endif
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};
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static int uart_xmc4xxx_poll_in(const struct device *dev, unsigned char *c)
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{
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const struct uart_xmc4xxx_config *config = dev->config;
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bool fifo_empty;
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if (config->fifo_rx_size > 0) {
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fifo_empty = XMC_USIC_CH_RXFIFO_IsEmpty(config->uart);
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} else {
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fifo_empty = !XMC_USIC_CH_GetReceiveBufferStatus(config->uart);
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}
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if (fifo_empty) {
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return -1;
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}
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*c = (unsigned char)XMC_UART_CH_GetReceivedData(config->uart);
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return 0;
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}
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static void uart_xmc4xxx_poll_out(const struct device *dev, unsigned char c)
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{
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const struct uart_xmc4xxx_config *config = dev->config;
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/* XMC_UART_CH_Transmit() only blocks for UART to finish transmitting */
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/* when fifo is not used */
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while (config->fifo_tx_size > 0 && XMC_USIC_CH_TXFIFO_IsFull(config->uart)) {
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}
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XMC_UART_CH_Transmit(config->uart, c);
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}
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#define MAX_FIFO_SIZE 64
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static int uart_xmc4xxx_init(const struct device *dev)
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{
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int ret;
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const struct uart_xmc4xxx_config *config = dev->config;
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struct uart_xmc4xxx_data *data = dev->data;
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uint8_t fifo_offset = config->fifo_start_offset;
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data->config.data_bits = 8U;
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data->config.stop_bits = 1U;
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XMC_UART_CH_Init(config->uart, &(data->config));
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if (config->fifo_tx_size > 0) {
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/* fifos need to be aligned on fifo size */
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fifo_offset = ROUND_UP(fifo_offset, BIT(config->fifo_tx_size));
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XMC_USIC_CH_TXFIFO_Configure(config->uart, fifo_offset, config->fifo_tx_size, 1);
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fifo_offset += BIT(config->fifo_tx_size);
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}
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if (config->fifo_rx_size > 0) {
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/* fifos need to be aligned on fifo size */
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fifo_offset = ROUND_UP(fifo_offset, BIT(config->fifo_rx_size));
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XMC_USIC_CH_RXFIFO_Configure(config->uart, fifo_offset, config->fifo_rx_size, 0);
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fifo_offset += BIT(config->fifo_rx_size);
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}
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if (fifo_offset > MAX_FIFO_SIZE) {
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return -EINVAL;
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}
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/* Connect UART RX to logical 1. It is connected to proper pin after pinctrl is applied */
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XMC_UART_CH_SetInputSource(config->uart, XMC_UART_CH_INPUT_RXD, 0x7);
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/* Start the UART before pinctrl, because the USIC is driving the TX line */
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/* low in off state */
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XMC_UART_CH_Start(config->uart);
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ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
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if (ret < 0) {
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return ret;
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}
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/* Connect UART RX to the target pin */
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XMC_UART_CH_SetInputSource(config->uart, XMC_UART_CH_INPUT_RXD,
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config->input_src);
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#if defined(CONFIG_UART_INTERRUPT_DRIVEN)
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config->irq_config_func(dev);
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#endif
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return 0;
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}
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#if defined(CONFIG_UART_INTERRUPT_DRIVEN)
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static void uart_xmc4xxx_isr(void *arg)
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{
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const struct device *dev = arg;
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struct uart_xmc4xxx_data *data = dev->data;
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if (data->user_cb) {
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data->user_cb(dev, data->user_data);
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}
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}
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static int uart_xmc4xxx_fifo_fill(const struct device *dev, const uint8_t *tx_data, int len)
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{
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const struct uart_xmc4xxx_config *config = dev->config;
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int i = 0;
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for (i = 0; i < len; i++) {
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bool fifo_full;
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XMC_UART_CH_Transmit(config->uart, tx_data[0]);
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if (config->fifo_tx_size == 0) {
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return 1;
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}
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fifo_full = XMC_USIC_CH_TXFIFO_IsFull(config->uart);
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if (fifo_full) {
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return i + 1;
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}
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}
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return i;
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}
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static int uart_xmc4xxx_fifo_read(const struct device *dev, uint8_t *rx_data, const int size)
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{
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const struct uart_xmc4xxx_config *config = dev->config;
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int i;
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for (i = 0; i < size; i++) {
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bool fifo_empty;
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if (config->fifo_rx_size > 0) {
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fifo_empty = XMC_USIC_CH_RXFIFO_IsEmpty(config->uart);
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} else {
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fifo_empty = !XMC_USIC_CH_GetReceiveBufferStatus(config->uart);
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}
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if (fifo_empty) {
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break;
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}
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rx_data[i] = XMC_UART_CH_GetReceivedData(config->uart);
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}
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return i;
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}
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static void uart_xmc4xxx_irq_tx_enable(const struct device *dev)
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{
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const struct uart_xmc4xxx_config *config = dev->config;
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const struct uart_xmc4xxx_data *data = dev->data;
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if (config->fifo_tx_size > 0) {
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/* wait till the fifo has at least 1 byte free */
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while (XMC_USIC_CH_TXFIFO_IsFull(config->uart)) {
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}
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XMC_USIC_CH_TXFIFO_EnableEvent(config->uart,
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XMC_USIC_CH_TXFIFO_EVENT_CONF_STANDARD);
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} else {
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XMC_USIC_CH_EnableEvent(config->uart, XMC_USIC_CH_EVENT_TRANSMIT_BUFFER);
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}
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XMC_USIC_CH_TriggerServiceRequest(config->uart, data->service_request);
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}
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static void uart_xmc4xxx_irq_tx_disable(const struct device *dev)
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{
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const struct uart_xmc4xxx_config *config = dev->config;
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if (config->fifo_tx_size > 0) {
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XMC_USIC_CH_TXFIFO_DisableEvent(config->uart,
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XMC_USIC_CH_TXFIFO_EVENT_CONF_STANDARD);
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} else {
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XMC_USIC_CH_DisableEvent(config->uart, XMC_USIC_CH_EVENT_TRANSMIT_BUFFER);
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}
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}
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static int uart_xmc4xxx_irq_tx_ready(const struct device *dev)
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{
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const struct uart_xmc4xxx_config *config = dev->config;
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if (config->fifo_tx_size > 0) {
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return !XMC_USIC_CH_TXFIFO_IsFull(config->uart);
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} else {
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return XMC_USIC_CH_GetTransmitBufferStatus(config->uart) ==
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XMC_USIC_CH_TBUF_STATUS_IDLE;
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}
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}
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static void uart_xmc4xxx_irq_rx_enable(const struct device *dev)
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{
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const struct uart_xmc4xxx_config *config = dev->config;
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uint32_t recv_status;
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if (config->fifo_rx_size > 0) {
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XMC_USIC_CH_RXFIFO_Flush(config->uart);
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XMC_USIC_CH_RXFIFO_SetSizeTriggerLimit(config->uart, config->fifo_rx_size, 0);
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#if CONFIG_UART_XMC4XXX_RX_FIFO_INT_TRIGGER
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config->uart->RBCTR |= BIT(USIC_CH_RBCTR_SRBTEN_Pos);
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#endif
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XMC_USIC_CH_RXFIFO_EnableEvent(config->uart,
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XMC_USIC_CH_RXFIFO_EVENT_CONF_STANDARD |
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XMC_USIC_CH_RXFIFO_EVENT_CONF_ALTERNATE);
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} else {
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/* flush out any received bytes while the uart rx irq was disabled */
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recv_status = XMC_USIC_CH_GetReceiveBufferStatus(config->uart);
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if (recv_status & USIC_CH_RBUFSR_RDV0_Msk) {
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XMC_UART_CH_GetReceivedData(config->uart);
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}
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if (recv_status & USIC_CH_RBUFSR_RDV1_Msk) {
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XMC_UART_CH_GetReceivedData(config->uart);
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}
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XMC_USIC_CH_EnableEvent(config->uart, XMC_USIC_CH_EVENT_STANDARD_RECEIVE |
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XMC_USIC_CH_EVENT_ALTERNATIVE_RECEIVE);
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}
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}
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static void uart_xmc4xxx_irq_rx_disable(const struct device *dev)
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{
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const struct uart_xmc4xxx_config *config = dev->config;
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if (config->fifo_rx_size > 0) {
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XMC_USIC_CH_RXFIFO_DisableEvent(config->uart,
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XMC_USIC_CH_RXFIFO_EVENT_CONF_STANDARD |
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XMC_USIC_CH_RXFIFO_EVENT_CONF_ALTERNATE);
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} else {
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XMC_USIC_CH_DisableEvent(config->uart, XMC_USIC_CH_EVENT_STANDARD_RECEIVE |
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XMC_USIC_CH_EVENT_ALTERNATIVE_RECEIVE);
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}
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}
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static int uart_xmc4xxx_irq_rx_ready(const struct device *dev)
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{
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const struct uart_xmc4xxx_config *config = dev->config;
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if (config->fifo_rx_size > 0) {
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return !XMC_USIC_CH_RXFIFO_IsEmpty(config->uart);
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} else {
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return XMC_USIC_CH_GetReceiveBufferStatus(config->uart);
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}
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}
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static void uart_xmc4xxx_irq_callback_set(const struct device *dev,
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uart_irq_callback_user_data_t cb, void *user_data)
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{
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struct uart_xmc4xxx_data *data = dev->data;
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data->user_cb = cb;
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data->user_data = user_data;
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}
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#define NVIC_ISPR_BASE 0xe000e200u
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static int uart_xmc4xxx_irq_is_pending(const struct device *dev)
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{
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const struct uart_xmc4xxx_config *config = dev->config;
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uint32_t irq_num = config->irq_num;
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uint32_t setpend;
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/* the NVIC_ISPR_BASE address stores info which interrupts are pending */
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/* bit 0 -> irq 0, bit 1 -> irq 1,... */
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setpend = *((uint32_t *)(NVIC_ISPR_BASE) + irq_num / 32);
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irq_num = irq_num & 0x1f; /* take modulo 32 */
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return (setpend & BIT(irq_num)) > 0;
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}
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#endif
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static const struct uart_driver_api uart_xmc4xxx_driver_api = {
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.poll_in = uart_xmc4xxx_poll_in,
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.poll_out = uart_xmc4xxx_poll_out,
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#if defined(CONFIG_UART_INTERRUPT_DRIVEN)
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.fifo_fill = uart_xmc4xxx_fifo_fill,
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.fifo_read = uart_xmc4xxx_fifo_read,
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.irq_tx_enable = uart_xmc4xxx_irq_tx_enable,
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.irq_tx_disable = uart_xmc4xxx_irq_tx_disable,
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.irq_tx_ready = uart_xmc4xxx_irq_tx_ready,
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.irq_rx_enable = uart_xmc4xxx_irq_rx_enable,
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.irq_rx_disable = uart_xmc4xxx_irq_rx_disable,
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.irq_rx_ready = uart_xmc4xxx_irq_rx_ready,
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.irq_callback_set = uart_xmc4xxx_irq_callback_set,
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.irq_is_pending = uart_xmc4xxx_irq_is_pending,
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#endif
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};
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#define USIC_IRQ_MIN 84
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#define USIC_IRQ_MAX 101
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#define IRQS_PER_USIC 6
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#if defined(CONFIG_UART_INTERRUPT_DRIVEN)
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#define XMC4XXX_IRQ_HANDLER(index) \
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static void uart_xmc4xxx_irq_setup_##index(const struct device *dev) \
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{ \
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const struct uart_xmc4xxx_config *config = dev->config; \
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struct uart_xmc4xxx_data *data = dev->data; \
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\
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__ASSERT(config->irq_num >= USIC_IRQ_MIN && config->irq_num <= USIC_IRQ_MAX, \
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"Invalid irq number\n"); \
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\
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data->service_request = (config->irq_num - USIC_IRQ_MIN) % IRQS_PER_USIC; \
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\
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if (config->fifo_tx_size > 0) { \
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XMC_USIC_CH_TXFIFO_SetInterruptNodePointer( \
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config->uart, XMC_USIC_CH_TXFIFO_INTERRUPT_NODE_POINTER_STANDARD, \
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data->service_request); \
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} else { \
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XMC_USIC_CH_SetInterruptNodePointer( \
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config->uart, XMC_USIC_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER, \
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data->service_request); \
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} \
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\
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if (config->fifo_rx_size > 0) { \
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XMC_USIC_CH_RXFIFO_SetInterruptNodePointer( \
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config->uart, XMC_USIC_CH_RXFIFO_INTERRUPT_NODE_POINTER_STANDARD, \
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data->service_request); \
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XMC_USIC_CH_RXFIFO_SetInterruptNodePointer( \
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config->uart, XMC_USIC_CH_RXFIFO_INTERRUPT_NODE_POINTER_ALTERNATE, \
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data->service_request); \
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} else { \
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XMC_USIC_CH_SetInterruptNodePointer( \
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config->uart, XMC_USIC_CH_INTERRUPT_NODE_POINTER_RECEIVE, \
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data->service_request); \
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\
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XMC_USIC_CH_SetInterruptNodePointer( \
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config->uart, XMC_USIC_CH_INTERRUPT_NODE_POINTER_ALTERNATE_RECEIVE,\
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data->service_request); \
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} \
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\
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IRQ_CONNECT(DT_INST_IRQ_BY_NAME(index, tx_rx, irq), \
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DT_INST_IRQ_BY_NAME(index, tx_rx, priority), uart_xmc4xxx_isr, \
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DEVICE_DT_INST_GET(index), 0); \
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irq_enable(DT_INST_IRQ_BY_NAME(index, tx_rx, irq)); \
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}
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#define XMC4XXX_IRQ_STRUCT_INIT(index) \
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.irq_config_func = uart_xmc4xxx_irq_setup_##index, \
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.irq_num = DT_INST_IRQ_BY_NAME(index, tx_rx, irq),
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#else
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#define XMC4XXX_IRQ_HANDLER(index)
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#define XMC4XXX_IRQ_STRUCT_INIT(index)
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#endif
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#define XMC4XXX_INIT(index) \
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PINCTRL_DT_INST_DEFINE(index); \
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XMC4XXX_IRQ_HANDLER(index) \
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static struct uart_xmc4xxx_data xmc4xxx_data_##index = { \
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.config.baudrate = DT_INST_PROP(index, current_speed) \
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}; \
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\
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static const struct uart_xmc4xxx_config xmc4xxx_config_##index = { \
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.uart = (XMC_USIC_CH_t *)DT_INST_REG_ADDR(index), \
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.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(index), \
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.input_src = DT_INST_ENUM_IDX(index, input_src), \
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XMC4XXX_IRQ_STRUCT_INIT(index) \
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.fifo_start_offset = DT_INST_PROP(index, fifo_start_offset), \
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.fifo_tx_size = DT_INST_ENUM_IDX(index, fifo_tx_size), \
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.fifo_rx_size = DT_INST_ENUM_IDX(index, fifo_rx_size), \
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}; \
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\
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DEVICE_DT_INST_DEFINE(index, &uart_xmc4xxx_init, \
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NULL, \
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&xmc4xxx_data_##index, \
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&xmc4xxx_config_##index, PRE_KERNEL_1, \
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CONFIG_SERIAL_INIT_PRIORITY, \
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&uart_xmc4xxx_driver_api);
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DT_INST_FOREACH_STATUS_OKAY(XMC4XXX_INIT)
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