54b6d26242
This adds an spi master mode driver via bitbanged gpio. Only syncronous transfers are implemented. Clock signal timing is accomplished via busy waits, the gpios are manipulated via the standard gpio interface; these two factors limit the frequency at which it can operate - but here a simple and generic implementation was chosen over performance. The driver supports the various clock polarity and phase configurations, and can also work with word sizes which are non multiples of 8bits, currently up to 16 bits. A sample program is also added demonstrating basic use of the driver with 9bit data words. Signed-off-by: Marc Reilly <marc@cpdesign.com.au>
6 lines
72 B
Plaintext
6 lines
72 B
Plaintext
CONFIG_STDOUT_CONSOLE=y
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CONFIG_SPI=y
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CONFIG_SPI_BITBANG=y
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CONFIG_LOG=y
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