zephyr/arch/xtensa
Daniel Leung 81ea43692c xtensa: mmu: send IPI to invalidate TLBs on other CPUs
After changing content of page table(s), it is needed to notify
the other CPUs that the page table(s) have been changed so they
can do the necessary steps to use the updated version. Note that
the actual way to send IPI is SoC specific as Xtensa does not
have a common way to do this at the moment.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2023-11-21 15:49:48 +01:00
..
core xtensa: mmu: send IPI to invalidate TLBs on other CPUs 2023-11-21 15:49:48 +01:00
include xtensa: mmu: allocate scratch registers for MMU 2023-11-21 15:49:48 +01:00
CMakeLists.txt xtensa: userspace: Add syscall for user exception 2023-11-21 15:49:48 +01:00
Kconfig xtensa: Enable userspace 2023-11-21 15:49:48 +01:00