Henrik Brix Andersen bc69500b0e drivers: can: stm32h7: fdcan: add support for domain clock and divider ... Add support for specifying the domain/kernel clock along with a common clock divider for the STM32H7 CAN controller driver via devicetree. Previously, the driver only supported using the PLL1_Q clock for domain/kernel clock, but now the driver defaults to the HSE clock, which is the chip default. Update existing boards to continue to use the PLL1_Q clock. Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>		2024-01-10 20:59:55 -05:00
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doc	boards: arm: doc: fix small typo	2024-01-09 10:04:11 +01:00
support
arduino_r3_connector.dtsi
board.cmake	boards: stm32h7: Update openocd runner to specify target handle	2022-05-24 08:52:16 -07:00
Kconfig.board
Kconfig.defconfig	boards: stop using kscan for LVGL touch input	2023-09-05 10:05:50 +02:00
stm32h7b3i_dk.dts	drivers: can: stm32h7: fdcan: add support for domain clock and divider	2024-01-10 20:59:55 -05:00
stm32h7b3i_dk.yaml	boards: add vendor to board yaml	2023-09-22 09:29:36 +02:00
stm32h7b3i_dk_defconfig