86a67faeaa
The whole mechanism of IRQ table generation is build around the assumption that the IRQ vector table contains an array of addresses the PC will be assigned to when the corresponding interrupt is triggered. While this is correct for the majority of architectures (ARM, RISCV with CLIC in vectored mode, etc...) this is not valid in general (for example RISCV with CLINT/HLINT in vectored mode). In this alternative format for the IRQ vector table, the pc will get assigned by the hardware to the address of the vector table index corresponding to the interrupt ID. From the vector table index, a subsequent jump will occur from there to service the interrupt. This means that the IRQ vector table contains an opcode that is a jump instruction to a specific location instead of the address of the location itself. This patch is introducing support for this alternative IRQ vector table format. The user can now select one format or the other one by acting on IRQ_VECTOR_TABLE_JUMP_BY_ADDRESS or IRQ_VECTOR_TABLE_JUMP_BY_CODE Kconfig symbols. Signed-off-by: Carlo Caione <ccaione@baylibre.com> |
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| .. | ||
| CMakeLists.txt | ||
| gen_isr_tables.py | ||
| isr_tables.c | ||
| Kconfig | ||
| nocache.ld | ||
| ramfunc.ld | ||
| rom_start_offset.ld | ||
| semihost.c | ||
| sw_isr_common.c | ||
| timing.c | ||